From patchwork Thu Feb 10 18:13:10 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: York Sun X-Patchwork-Id: 82642 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id A3AAAB7109 for ; Fri, 11 Feb 2011 05:13:40 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DD6FF28269; Thu, 10 Feb 2011 19:13:38 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MhwP69I++erI; Thu, 10 Feb 2011 19:13:38 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9E60B2826A; Thu, 10 Feb 2011 19:13:36 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 156BC2826A for ; Thu, 10 Feb 2011 19:13:35 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Yp2sCR55TH+X for ; Thu, 10 Feb 2011 19:13:33 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from AM1EHSOBE001.bigfish.com (am1ehsobe001.messaging.microsoft.com [213.199.154.204]) by theia.denx.de (Postfix) with ESMTPS id 0A40C28269 for ; Thu, 10 Feb 2011 19:13:31 +0100 (CET) Received: from mail77-am1-R.bigfish.com (10.3.201.254) by AM1EHSOBE001.bigfish.com (10.3.204.21) with Microsoft SMTP Server id 14.1.225.8; Thu, 10 Feb 2011 18:13:31 +0000 Received: from mail77-am1 (localhost.localdomain [127.0.0.1]) by mail77-am1-R.bigfish.com (Postfix) with ESMTP id 25061104876A for ; Thu, 10 Feb 2011 18:13:31 +0000 (UTC) X-SpamScore: -5 X-BigFish: VS-5(zz1803Mzz1202hzz8275bhz2dh2a8h668h64h) X-Spam-TCS-SCL: 3:0 X-Forefront-Antispam-Report: KIP:(null); UIP:(null); IPVD:NLI; H:az33egw01.freescale.net; RD:az33egw01.freescale.net; EFVD:NLI Received: from mail77-am1 (localhost.localdomain [127.0.0.1]) by mail77-am1 (MessageSwitch) id 1297361610978986_18290; Thu, 10 Feb 2011 18:13:30 +0000 (UTC) Received: from AM1EHSMHS004.bigfish.com (unknown [10.3.201.247]) by mail77-am1.bigfish.com (Postfix) with ESMTP id ED32FD98050 for ; Thu, 10 Feb 2011 18:13:30 +0000 (UTC) Received: from az33egw01.freescale.net (192.88.158.102) by AM1EHSMHS004.bigfish.com (10.3.207.104) with Microsoft SMTP Server (TLS) id 14.1.225.8; Thu, 10 Feb 2011 18:13:15 +0000 Received: from az33smr01.freescale.net (az33smr01.freescale.net [10.64.34.199]) by az33egw01.freescale.net (8.14.3/8.14.3) with ESMTP id p1AIDD99020235 for ; Thu, 10 Feb 2011 11:13:13 -0700 (MST) Received: from localhost.localdomain (mvp-10-214-72-32.am.freescale.net [10.214.72.32]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p1AIDAl1026960; Thu, 10 Feb 2011 12:13:11 -0600 (CST) From: York Sun To: Date: Thu, 10 Feb 2011 10:13:10 -0800 Message-ID: <1297361590-8953-1-git-send-email-yorksun@freescale.com> X-Mailer: git-send-email 1.7.0.4 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Subject: [U-Boot] [PATCH] powerpc/8xxx: Add additional cycle to write-to-read turnaound for DDR3 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de When DDR data rate is higher than 1200MT/s or controller interleaving is enabled, additional cycle for write-to-read turnaround is needed to satisfy dynamic ODT timing. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 3 +++ arch/powerpc/cpu/mpc8xxx/ddr/ddr.h | 2 +- 2 files changed, 4 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index c3e1d76..936c195 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -236,9 +236,12 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, * tAXPD=1, need design to confirm. */ int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */ + unsigned int data_rate = fsl_ddr_get_mem_data_rate(); tmrd_mclk = 4; /* set the turnaround time */ trwt_mclk = 1; + if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving)) + twrt_mclk = 1; if (popts->dynamic_power == 0) { /* powerdown is not used */ act_pd_exit_mclk = 1; diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h index 35b60a0..c7c12c1 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h @@ -80,5 +80,5 @@ extern void check_interleaving_options(fsl_ddr_info_t *pinfo); extern unsigned int mclk_to_picos(unsigned int mclk); extern unsigned int get_memory_clk_period_ps(void); extern unsigned int picos_to_mclk(unsigned int picos); - +extern unsigned int fsl_ddr_get_mem_data_rate(void); #endif