diff mbox series

[U-Boot] ARC: HSDK: introduce CREG GPIO driver

Message ID 20171013132143.26340-1-Eugeniy.Paltsev@synopsys.com
State Superseded
Delegated to: Alexey Brodkin
Headers show
Series [U-Boot] ARC: HSDK: introduce CREG GPIO driver | expand

Commit Message

Eugeniy Paltsev Oct. 13, 2017, 1:21 p.m. UTC 
The HSDK can manage some pins via CREG registers block.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
---
 MAINTAINERS                   |   6 +++
 drivers/gpio/Kconfig          |   7 +++
 drivers/gpio/Makefile         |   1 +
 drivers/gpio/hsdk-creg-gpio.c | 109 ++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 123 insertions(+)
 create mode 100644 drivers/gpio/hsdk-creg-gpio.c

Comments

Alexey Brodkin Oct. 13, 2017, 1:33 p.m. UTC | #1 
Hi Tom,

On Fri, 2017-10-13 at 16:21 +0300, Eugeniy Paltsev wrote:
> The HSDK can manage some pins via CREG registers block.

> 

> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>

> ---

>  MAINTAINERS                   |   6 +++

>  drivers/gpio/Kconfig          |   7 +++

>  drivers/gpio/Makefile         |   1 +

>  drivers/gpio/hsdk-creg-gpio.c | 109 ++++++++++++++++++++++++++++++++++++++++++

>  4 files changed, 123 insertions(+)

>  create mode 100644 drivers/gpio/hsdk-creg-gpio.c


I'm wondering if this one should go through my tree as this
is for one of our Synopsys ARC devboards or GPIO stuff usually
goes through some other tree?

-Alexey
Tom Rini Oct. 13, 2017, 1:46 p.m. UTC | #2 
On Fri, Oct 13, 2017 at 01:33:22PM +0000, Alexey Brodkin wrote:
> Hi Tom,
> 
> On Fri, 2017-10-13 at 16:21 +0300, Eugeniy Paltsev wrote:
> > The HSDK can manage some pins via CREG registers block.
> > 
> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
> > ---
> >  MAINTAINERS                   |   6 +++
> >  drivers/gpio/Kconfig          |   7 +++
> >  drivers/gpio/Makefile         |   1 +
> >  drivers/gpio/hsdk-creg-gpio.c | 109 ++++++++++++++++++++++++++++++++++++++++++
> >  4 files changed, 123 insertions(+)
> >  create mode 100644 drivers/gpio/hsdk-creg-gpio.c
> 
> I'm wondering if this one should go through my tree as this
> is for one of our Synopsys ARC devboards or GPIO stuff usually
> goes through some other tree?

The ARC tree is fine, but it's a bit late posting for this release.
Thanks!
Alexey Brodkin Oct. 13, 2017, 1:55 p.m. UTC | #3 
Hi Tom,

On Fri, 2017-10-13 at 09:46 -0400, Tom Rini wrote:
> On Fri, Oct 13, 2017 at 01:33:22PM +0000, Alexey Brodkin wrote:

> > 

> > Hi Tom,

> > 

> > On Fri, 2017-10-13 at 16:21 +0300, Eugeniy Paltsev wrote:

> > > 

> > > The HSDK can manage some pins via CREG registers block.

> > > 

> > > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>

> > > ---

> > >  MAINTAINERS                   |   6 +++

> > >  drivers/gpio/Kconfig          |   7 +++

> > >  drivers/gpio/Makefile         |   1 +

> > >  drivers/gpio/hsdk-creg-gpio.c | 109 ++++++++++++++++++++++++++++++++++++++++++

> > >  4 files changed, 123 insertions(+)

> > >  create mode 100644 drivers/gpio/hsdk-creg-gpio.c

> > 

> > I'm wondering if this one should go through my tree as this

> > is for one of our Synopsys ARC devboards or GPIO stuff usually

> > goes through some other tree?

> 

> The ARC tree is fine, but it's a bit late posting for this release.


So should I keep this one in "next" branch of my tree before v2017.11
gets cut?

-Alexey
Tom Rini Oct. 13, 2017, 1:55 p.m. UTC | #4 
On Fri, Oct 13, 2017 at 01:55:28PM +0000, Alexey Brodkin wrote:
> Hi Tom,
> 
> On Fri, 2017-10-13 at 09:46 -0400, Tom Rini wrote:
> > On Fri, Oct 13, 2017 at 01:33:22PM +0000, Alexey Brodkin wrote:
> > > 
> > > Hi Tom,
> > > 
> > > On Fri, 2017-10-13 at 16:21 +0300, Eugeniy Paltsev wrote:
> > > > 
> > > > The HSDK can manage some pins via CREG registers block.
> > > > 
> > > > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
> > > > ---
> > > >  MAINTAINERS                   |   6 +++
> > > >  drivers/gpio/Kconfig          |   7 +++
> > > >  drivers/gpio/Makefile         |   1 +
> > > >  drivers/gpio/hsdk-creg-gpio.c | 109 ++++++++++++++++++++++++++++++++++++++++++
> > > >  4 files changed, 123 insertions(+)
> > > >  create mode 100644 drivers/gpio/hsdk-creg-gpio.c
> > > 
> > > I'm wondering if this one should go through my tree as this
> > > is for one of our Synopsys ARC devboards or GPIO stuff usually
> > > goes through some other tree?
> > 
> > The ARC tree is fine, but it's a bit late posting for this release.
> 
> So should I keep this one in "next" branch of my tree before v2017.11
> gets cut?

Yes, thanks.
Alexey Brodkin Oct. 16, 2017, 12:30 p.m. UTC | #5 
Hi Eugeniy,

On Fri, 2017-10-13 at 16:21 +0300, Eugeniy Paltsev wrote:
> The HSDK can manage some pins via CREG registers block.

> 

> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>

> ---

>  MAINTAINERS                   |   6 +++

>  drivers/gpio/Kconfig          |   7 +++

>  drivers/gpio/Makefile         |   1 +

>  drivers/gpio/hsdk-creg-gpio.c | 109 ++++++++++++++++++++++++++++++++++++++++++

>  4 files changed, 123 insertions(+)

>  create mode 100644 drivers/gpio/hsdk-creg-gpio.c


I've got this one applied on top of today's upstream master and with
enabled HSDK GPIO driver I'm seeing this build failure:
------------------------------>8-----------------------------
  LD      cmd/built-in.o
drivers/gpio/hsdk-creg-gpio.c: In function ‘hsdk_creg_gpio_direction_input’:
drivers/gpio/hsdk-creg-gpio.c:55:2: warning: implicit declaration of function ‘error’ [-Wimplicit-function-declaration]
  error("hsdk-creg-gpio can't be used as input!\n");
  ^~~~~
  LD      drivers/gpio/built-in.o
  LD      common/built-in.o
make[2]: 'arch/arc/dts/hsdk.dtb' is up to date.
  CC      lib/display_options.o
  LD      lib/built-in.o
  LD      u-boot
drivers/gpio/built-in.o: In function `hsdk_creg_gpio_direction_input':
.../u-boot/drivers/gpio/hsdk-creg-gpio.c:55: undefined reference to `error'
.../u-boot/drivers/gpio/hsdk-creg-gpio.c:55: undefined reference to `error'
Makefile:1256: recipe for target 'u-boot' failed
------------------------------>8-----------------------------

Could you please check what's wrong there and fix it.

-Alexey
diff mbox series

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index 04acf2b..df662aa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -59,6 +59,12 @@  S:	Maintained
 T:	git git://git.denx.de/u-boot-arc.git
 F:	arch/arc/
 
+ARC HSDK CREG GPIO
+M:	Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+S:	Maintained
+L:	uboot-snps-arc@synopsys.com
+F:	drivers/gpio/hsdk-creg-gpio.c
+
 ARM
 M:	Albert Aribaud <albert.u.boot@aribaud.net>
 S:	Maintained
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index ffeda94..9928911 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -80,6 +80,13 @@  config IMX_RGPIO2P
 	help
 	  This driver supports i.MX7ULP Rapid GPIO2P controller.
 
+config HSDK_CREG_GPIO
+	bool "HSDK CREG GPIO griver"
+	depends on DM
+	default n
+	help
+	  This driver supports CREG GPIOs on Synopsys HSDK SOC.
+
 config LPC32XX_GPIO
 	bool "LPC32XX GPIO driver"
 	depends on DM
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 1396467..c7efc4c 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -53,6 +53,7 @@  obj-$(CONFIG_GPIO_UNIPHIER)	+= gpio-uniphier.o
 obj-$(CONFIG_ZYNQ_GPIO)		+= zynq_gpio.o
 obj-$(CONFIG_VYBRID_GPIO)	+= vybrid_gpio.o
 obj-$(CONFIG_HIKEY_GPIO)	+= hi6220_gpio.o
+obj-$(CONFIG_HSDK_CREG_GPIO)	+= hsdk-creg-gpio.o
 obj-$(CONFIG_IMX_RGPIO2P)	+= imx_rgpio2p.o
 obj-$(CONFIG_PIC32_GPIO)	+= pic32_gpio.o
 obj-$(CONFIG_MVEBU_GPIO)	+= mvebu_gpio.o
diff --git a/drivers/gpio/hsdk-creg-gpio.c b/drivers/gpio/hsdk-creg-gpio.c
new file mode 100644
index 0000000..bfbfe5b
--- /dev/null
+++ b/drivers/gpio/hsdk-creg-gpio.c
@@ -0,0 +1,109 @@ 
+/*
+ * Synopsys HSDK SDP Generic PLL clock driver
+ *
+ * Copyright (C) 2017 Synopsys
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm-generic/gpio.h>
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define HSDK_CREG_MAX_GPIO	8
+
+#define GPIO_ACTIVATE		0x2
+#define GPIO_DEACTIVATE		0x3
+#define GPIO_PIN_MASK		0x3
+#define BIT_PER_GPIO		2
+
+struct hsdk_creg_gpio {
+	uint32_t *regs;
+};
+
+static int hsdk_creg_gpio_set_value(struct udevice *dev, unsigned oft, int val)
+{
+	struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
+	uint32_t reg = readl(hcg->regs);
+	uint32_t cmd = val ? GPIO_DEACTIVATE : GPIO_ACTIVATE;
+
+	reg &= ~(GPIO_PIN_MASK << (oft * BIT_PER_GPIO));
+	reg |=  (cmd << (oft * BIT_PER_GPIO));
+
+	writel(reg, hcg->regs);
+
+	return 0;
+}
+
+static int hsdk_creg_gpio_direction_output(struct udevice *dev, unsigned oft,
+					   int val)
+{
+	hsdk_creg_gpio_set_value(dev, oft, val);
+
+	return 0;
+}
+
+static int hsdk_creg_gpio_direction_input(struct udevice *dev, unsigned oft)
+{
+	error("hsdk-creg-gpio can't be used as input!\n");
+
+	return -ENOTSUPP;
+}
+
+static int hsdk_creg_gpio_get_value(struct udevice *dev, unsigned int oft)
+{
+	struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
+	uint32_t val = readl(hcg->regs);
+
+	val = (val >> (oft * BIT_PER_GPIO)) & GPIO_PIN_MASK;
+	return (val == GPIO_DEACTIVATE) ? 1 : 0;
+}
+
+static const struct dm_gpio_ops hsdk_creg_gpio_ops = {
+	.direction_output	= hsdk_creg_gpio_direction_output,
+	.direction_input	= hsdk_creg_gpio_direction_input,
+	.set_value		= hsdk_creg_gpio_set_value,
+	.get_value		= hsdk_creg_gpio_get_value,
+};
+
+static int hsdk_creg_gpio_probe(struct udevice *dev)
+{
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
+
+	hcg->regs = (uint32_t *)devfdt_get_addr_ptr(dev);
+
+	uc_priv->gpio_count = dev_read_u32_default(dev, "gpio-count", 1);
+	if (uc_priv->gpio_count > HSDK_CREG_MAX_GPIO)
+		uc_priv->gpio_count = HSDK_CREG_MAX_GPIO;
+
+	uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name");
+	if (!uc_priv->bank_name)
+		uc_priv->bank_name = dev_read_name(dev);
+
+	debug("%s GPIO [0x%p] controller with %d gpios probed\n",
+	      uc_priv->bank_name, hcg->regs, uc_priv->gpio_count);
+
+	return 0;
+}
+
+static const struct udevice_id hsdk_creg_gpio_ids[] = {
+	{ .compatible = "snps,hsdk-creg-gpio" },
+	{ }
+};
+
+U_BOOT_DRIVER(gpio_hsdk_creg) = {
+	.name	= "gpio_hsdk_creg",
+	.id	= UCLASS_GPIO,
+	.ops	= &hsdk_creg_gpio_ops,
+	.probe	= hsdk_creg_gpio_probe,
+	.of_match = hsdk_creg_gpio_ids,
+	.platdata_auto_alloc_size = sizeof(struct hsdk_creg_gpio),
+};