From patchwork Fri Oct 13 11:21:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 825415 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yD50g1lcGz9s82 for ; Fri, 13 Oct 2017 22:22:27 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yD50d6m0DzDrCQ for ; Fri, 13 Oct 2017 22:22:25 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=hegdevasant@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yD50D50dhzDqlv for ; Fri, 13 Oct 2017 22:22:04 +1100 (AEDT) Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v9DBKtgZ003063 for ; Fri, 13 Oct 2017 07:22:02 -0400 Received: from e06smtp14.uk.ibm.com (e06smtp14.uk.ibm.com [195.75.94.110]) by mx0a-001b2d01.pphosted.com with ESMTP id 2dju6jw49t-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Fri, 13 Oct 2017 07:22:01 -0400 Received: from localhost by e06smtp14.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 13 Oct 2017 12:21:58 +0100 Received: from d23av01.au.ibm.com (d23av01.au.ibm.com [9.190.234.96]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v9DBLt1I28967074 for ; Fri, 13 Oct 2017 11:21:57 GMT Received: from d23av01.au.ibm.com (localhost [127.0.0.1]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v9DBLuZ8018690 for ; Fri, 13 Oct 2017 22:21:56 +1100 Received: from hegdevasant.in.ibm.com ([9.199.177.209]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v9DBLq0H018557; Fri, 13 Oct 2017 22:21:54 +1100 From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Fri, 13 Oct 2017 16:51:19 +0530 X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171013112119.30164-1-hegdevasant@linux.vnet.ibm.com> References: <20171013112119.30164-1-hegdevasant@linux.vnet.ibm.com> X-TM-AS-MML: disable x-cbid: 17101311-0016-0000-0000-000004F57D0C X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17101311-0017-0000-0000-000028309B5E Message-Id: <20171013112119.30164-2-hegdevasant@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-10-13_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1710130159 Subject: [Skiboot] [PATCH v2 2/2] hdata: Parse SPD data X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Parse SPD data and populate device tree. list of properites parsing from SPD: ----------------------------------- [root@ltc-wspoon dimm@d00f]# lsprop . memory-id 0000000c (12) <-- DIMM type product-version 00000032 (50) <-- Module Revision Code device_type "memory-dimm-ddr4" serial-number 15d9acb6 (366587062) status "okay" size 00004000 (16384) phandle 000000bd (189) ibm,loc-code "UOPWR.0000000-Node0-DIMM7" part-number "36ASF2G72PZ-2G6B2 " reg 0000d007 (53255) name "dimm" manufacturer-id 0000802c (32812) <-- Vendor ID, we can get vendor name from this ID Also update documentation. Signed-off-by: Vasant Hegde --- Changes in v2: - Added few more properties - Updated documentation -Vasant doc/device-tree/memory-hierarchy.rst | 24 +++++++++++++++++ hdata/memory.c | 50 +++++++++++++++++++++++++++++++++++- 2 files changed, 73 insertions(+), 1 deletion(-) create mode 100644 doc/device-tree/memory-hierarchy.rst diff --git a/doc/device-tree/memory-hierarchy.rst b/doc/device-tree/memory-hierarchy.rst new file mode 100644 index 0000000..1da0c54 --- /dev/null +++ b/doc/device-tree/memory-hierarchy.rst @@ -0,0 +1,24 @@ +P9 memory hierarchy +------------------- +P9 Nimbus supports direct attached DDR memory through 4 DDR ports per side +of the processor. Device tree contains memory hierarchy so that one can +traverse from chip to DIMM like below: + + xscom@/mcbist@/mcs@/mca@/dimm@ + +Example of dimm node: +.. code-block:: dts + + dimm@d00e { + memory-id = <0xc>; /* DRAM Device Type. 0xc = DDR4 */ + product-version = <0x32>; /* Module Revision Code */ + device_type = "memory-dimm-ddr4"; + serial-number = <0x15d9ad1c>; + status = "okay"; + size = <0x4000>; + phandle = <0xd2>; + ibm,loc-code = "UOPWR.0000000-Node0-DIMM14"; + part-number = "36ASF2G72PZ-2G6B2 "; + reg = <0xd00e>; + manufacturer-id = <0x802c>; /* Vendor ID, we can get vendor name from this ID */ + }; diff --git a/hdata/memory.c b/hdata/memory.c index 74eedff..27dc559 100644 --- a/hdata/memory.c +++ b/hdata/memory.c @@ -319,16 +319,56 @@ static void vpd_add_ram_area(const struct HDIF_common_hdr *msarea) } } +static void vpd_parse_spd(struct dt_node *dimm, const char *spd, u32 size) +{ + u16 *vendor; + u32 *sn; + + /* SPD is too small */ + if (size < 512) { + prlog(PR_WARNING, "MSVPD: Invalid SPD size. " + "Expected 512 bytes, got %d\n", size); + return; + } + + /* Supports DDR4 format pasing only */ + if (spd[0x2] < 0xc) { + prlog(PR_WARNING, + "MSVPD: SPD format (%x) not supported\n", spd[0x2]); + return; + } + + dt_add_property_string(dimm, "device_type", "memory-dimm-ddr4"); + + /* DRAM device type */ + dt_add_property_cells(dimm, "memory-id", spd[0x2]); + + /* Module revision code */ + dt_add_property_cells(dimm, "product-version", spd[0x15d]); + + /* Serial number */ + sn = (u32 *)&spd[0x145]; + dt_add_property_cells(dimm, "serial-number", be32_to_cpu(*sn)); + + /* Part number */ + dt_add_property_nstr(dimm, "part-number", &spd[0x149], 20); + + /* Module manufacturer ID */ + vendor = (u16 *)&spd[0x140]; + dt_add_property_cells(dimm, "manufacturer-id", be16_to_cpu(*vendor)); +} + static void add_mca_dimm_info(struct dt_node *mca, const struct HDIF_common_hdr *msarea) { - unsigned int i; + unsigned int i, size; const struct HDIF_child_ptr *ramptr; const struct HDIF_common_hdr *ramarea; const struct spira_fru_id *fru_id; const struct HDIF_ram_area_id *ram_id; const struct HDIF_ram_area_size *ram_area_sz; struct dt_node *dimm; + const void *vpd_blob; ramptr = HDIF_child_arr(msarea, 0); if (!CHECK_SPPTR(ramptr)) { @@ -373,6 +413,14 @@ static void add_mca_dimm_info(struct dt_node *mca, dt_add_property_string(dimm, "status", "okay"); else dt_add_property_string(dimm, "status", "disabled"); + + vpd_blob = HDIF_get_idata(ramarea, 1, &size); + if (!CHECK_SPPTR(vpd_blob)) + continue; + if (vpd_valid(vpd_blob, size)) + vpd_data_parse(dimm, vpd_blob, size); + else + vpd_parse_spd(dimm, vpd_blob, size); } }