From patchwork Fri Oct 13 08:30:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 825282 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="nPyTG/Rs"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yD16J3kHhz9s82 for ; Fri, 13 Oct 2017 19:27:04 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 3C632C21FC5; Fri, 13 Oct 2017 08:26:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 39947C21FD9; Fri, 13 Oct 2017 08:26:11 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5211AC21FC1; Fri, 13 Oct 2017 08:25:48 +0000 (UTC) Received: from mail-qt0-f193.google.com (mail-qt0-f193.google.com [209.85.216.193]) by lists.denx.de (Postfix) with ESMTPS id A4A59C21F9D for ; Fri, 13 Oct 2017 08:25:44 +0000 (UTC) Received: by mail-qt0-f193.google.com with SMTP id f15so18219994qtf.7 for ; Fri, 13 Oct 2017 01:25:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=KrWTvuGaESxSoZFVE81dLPNSD29d0srowtDl0wypw48=; b=nPyTG/Rsz4haNRZ1wu4mNDkkuMHllEtiuPw6xAHAJ80LrlV1RKOoDI+9RS5mqWsnBO bET+MtGcV8b4DlwgJWzIcAuV9eu7pB1g+RA0Tz4DlNUzV0mc0NVLEg5jHEWBxZYvAQQH GKKpxiB6yvEKIScyDyQmnoCyjubr1LoNPEGpSUTNPeY7qeyRIKPSOLMmnHrNC5otreHX /UiXkchUM9IvsEA3D7vJ6c0cavWhIamLFwdFwsQhV6XxtoevZvl7OBL9xW/yBGPzD7Vy ugRVovzmdPmrM8u/71Dqg3TiuAkGq+1woI0/PNnVFlSnp+ULfHsbGWd0yxxkmRHiqbyI +0AA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=KrWTvuGaESxSoZFVE81dLPNSD29d0srowtDl0wypw48=; b=qQHeeD/DglqpE5w7smZxwYgn/f3rRqLU+AkJwpQcPtsG86ikmqnp0AOD9C7FA3qKUl wQI0EzsJ+30Qn4MPwbERl3YYUg31YH5ZJuoBxJnBTHhI6nwIen+Det4PN1DvFX3/hTVL 79OGbn0fB4u65qtRZFiEZu4luH2m9J/MtgWhusS3TRfPYJARB4gwqtlNA150eZjFJWN6 V0JgfIdAIgKhUDUfYGhmgUsGUj7pbFe/2lJVr9/aPxDQp4GkEBLJsayHdn1S5zGNI6Fh 4R2L9WredAtd/5oo9128veT1u9DGPBsOiSdCn4D9eDgZPdriOV45fLtKULmaP9NVpY7W nmew== X-Gm-Message-State: AMCzsaV8mInZVW6NSc3sKf0FjyxhNrRjqSAtwSSqYiYnzpg+LHV2xV2Y KdehZm6fg+e1sRZY2ECpDww= X-Google-Smtp-Source: ABhQp+SDp2O3qM2nNESIleYs8bdXaTzrVYsFIBkivf5PPQOLM9JoDvn8CbYJDP5JU5466og1ZQIeGA== X-Received: by 10.200.16.8 with SMTP id z8mr866263qti.61.1507883143522; Fri, 13 Oct 2017 01:25:43 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id f126sm228381qkd.37.2017.10.13.01.25.42 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 13 Oct 2017 01:25:42 -0700 (PDT) From: Bin Meng To: Simon Glass , Stefan Roese , George McCollister , U-Boot Mailing List Date: Fri, 13 Oct 2017 01:30:06 -0700 Message-Id: <1507883406-31390-3-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1507883406-31390-1-git-send-email-bmeng.cn@gmail.com> References: <1507883406-31390-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH 3/3] x86: baytrail: fsp: Move Azalia update codes to board X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Azalia configuration may be different across boards, hence it's not appropriate to do that in the SoC level. Instead, let's make the SoC update_fsp_azalia_configs() routine as a weak version, and do the actual work in the board codes. So far it seems only som-db5800-som-6867 board enables the Azalia. Move the original codes into som-db5800-som-6867.c. Signed-off-by: Bin Meng Reviewed-by: Stefan Roese --- arch/x86/cpu/baytrail/fsp_configs.c | 111 +-------------------- .../som-db5800-som-6867/som-db5800-som-6867.c | 111 +++++++++++++++++++++ 2 files changed, 113 insertions(+), 109 deletions(-) diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index 3052fb6..6b762e5 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -12,122 +12,15 @@ DECLARE_GLOBAL_DATA_PTR; -/* ALC262 Verb Table - 10EC0262 */ -static const u32 verb_table_data13[] = { - /* Pin Complex (NID 0x11) */ - 0x01171cf0, - 0x01171d11, - 0x01171e11, - 0x01171f41, - /* Pin Complex (NID 0x12) */ - 0x01271cf0, - 0x01271d11, - 0x01271e11, - 0x01271f41, - /* Pin Complex (NID 0x14) */ - 0x01471c10, - 0x01471d40, - 0x01471e01, - 0x01471f01, - /* Pin Complex (NID 0x15) */ - 0x01571cf0, - 0x01571d11, - 0x01571e11, - 0x01571f41, - /* Pin Complex (NID 0x16) */ - 0x01671cf0, - 0x01671d11, - 0x01671e11, - 0x01671f41, - /* Pin Complex (NID 0x18) */ - 0x01871c20, - 0x01871d98, - 0x01871ea1, - 0x01871f01, - /* Pin Complex (NID 0x19) */ - 0x01971c21, - 0x01971d98, - 0x01971ea1, - 0x01971f02, - /* Pin Complex (NID 0x1A) */ - 0x01a71c2f, - 0x01a71d30, - 0x01a71e81, - 0x01a71f01, - /* Pin Complex */ - 0x01b71c1f, - 0x01b71d40, - 0x01b71e21, - 0x01b71f02, - /* Pin Complex */ - 0x01c71cf0, - 0x01c71d11, - 0x01c71e11, - 0x01c71f41, - /* Pin Complex */ - 0x01d71c01, - 0x01d71dc6, - 0x01d71e14, - 0x01d71f40, - /* Pin Complex */ - 0x01e71cf0, - 0x01e71d11, - 0x01e71e11, - 0x01e71f41, - /* Pin Complex */ - 0x01f71cf0, - 0x01f71d11, - 0x01f71e11, - 0x01f71f41, -}; - -/* - * This needs to be in ROM since if we put it in CAR, FSP init loses it when - * it drops CAR. - * - * TODO(sjg@chromium.org): Move to device tree when FSP allows it - * - * VerbTable: (RealTek ALC262) - * Revision ID = 0xFF, support all steps - * Codec Verb Table For AZALIA - * Codec Address: CAd value (0/1/2) - * Codec Vendor: 0x10EC0262 - */ -static const struct azalia_verb_table azalia_verb_table[] = { - { - { - 0x10ec0262, - 0x0000, - 0xff, - 0x01, - 0x000b, - 0x0002, - }, - verb_table_data13 - } -}; - -const struct azalia_config azalia_config = { - .pme_enable = 1, - .docking_supported = 1, - .docking_attached = 0, - .hdmi_codec_enable = 1, - .azalia_v_ci_enable = 1, - .rsvdbits = 0, - .verb_table_num = 1, - .verb_table = azalia_verb_table, - .reset_wait_timer_ms = 300 -}; - /** * Override the FSP's Azalia configuration data * * @azalia: pointer to be updated to point to a ROM address where Azalia * configuration data is stored */ -static void update_fsp_azalia_configs(struct azalia_config **azalia) +__weak void update_fsp_azalia_configs(struct azalia_config **azalia) { - *azalia = (struct azalia_config *)&azalia_config; + *azalia = NULL; } /** diff --git a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c index 6158795..202e9875 100644 --- a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c +++ b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c @@ -6,6 +6,117 @@ */ #include +#include + +/* ALC262 Verb Table - 10EC0262 */ +static const u32 verb_table_data13[] = { + /* Pin Complex (NID 0x11) */ + 0x01171cf0, + 0x01171d11, + 0x01171e11, + 0x01171f41, + /* Pin Complex (NID 0x12) */ + 0x01271cf0, + 0x01271d11, + 0x01271e11, + 0x01271f41, + /* Pin Complex (NID 0x14) */ + 0x01471c10, + 0x01471d40, + 0x01471e01, + 0x01471f01, + /* Pin Complex (NID 0x15) */ + 0x01571cf0, + 0x01571d11, + 0x01571e11, + 0x01571f41, + /* Pin Complex (NID 0x16) */ + 0x01671cf0, + 0x01671d11, + 0x01671e11, + 0x01671f41, + /* Pin Complex (NID 0x18) */ + 0x01871c20, + 0x01871d98, + 0x01871ea1, + 0x01871f01, + /* Pin Complex (NID 0x19) */ + 0x01971c21, + 0x01971d98, + 0x01971ea1, + 0x01971f02, + /* Pin Complex (NID 0x1A) */ + 0x01a71c2f, + 0x01a71d30, + 0x01a71e81, + 0x01a71f01, + /* Pin Complex */ + 0x01b71c1f, + 0x01b71d40, + 0x01b71e21, + 0x01b71f02, + /* Pin Complex */ + 0x01c71cf0, + 0x01c71d11, + 0x01c71e11, + 0x01c71f41, + /* Pin Complex */ + 0x01d71c01, + 0x01d71dc6, + 0x01d71e14, + 0x01d71f40, + /* Pin Complex */ + 0x01e71cf0, + 0x01e71d11, + 0x01e71e11, + 0x01e71f41, + /* Pin Complex */ + 0x01f71cf0, + 0x01f71d11, + 0x01f71e11, + 0x01f71f41, +}; + +/* + * This needs to be in ROM since if we put it in CAR, FSP init loses it when + * it drops CAR. + * + * VerbTable: (RealTek ALC262) + * Revision ID = 0xFF, support all steps + * Codec Verb Table For AZALIA + * Codec Address: CAd value (0/1/2) + * Codec Vendor: 0x10EC0262 + */ +static const struct azalia_verb_table azalia_verb_table[] = { + { + { + 0x10ec0262, + 0x0000, + 0xff, + 0x01, + 0x000b, + 0x0002, + }, + verb_table_data13 + } +}; + +static const struct azalia_config azalia_config = { + .pme_enable = 1, + .docking_supported = 1, + .docking_attached = 0, + .hdmi_codec_enable = 1, + .azalia_v_ci_enable = 1, + .rsvdbits = 0, + .verb_table_num = 1, + .verb_table = azalia_verb_table, + .reset_wait_timer_ms = 300 +}; + +void update_fsp_azalia_configs(const struct azalia_config **azalia) +{ + *azalia = &azalia_config; +} int board_early_init_f(void) {