[U-Boot,v3,14/20] arm: socfpga: Improve comments for Intel SoCFPGA program header

Message ID 1507882137-27841-15-git-send-email-tien.fong.chee@intel.com
State Superseded
Delegated to: Marek Vasut
Headers show
Series
  • Add FPGA, SDRAM, SPL loadfs U-boot & booting to console
Related show

Commit Message

Chee, Tien Fong Oct. 13, 2017, 8:08 a.m.
From: Tien Fong Chee <tien.fong.chee@intel.com>

Adding some details about size in bytes to each section.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/include/mach/boot0.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Dinh Nguyen Oct. 20, 2017, 2:18 p.m. | #1
On 10/13/2017 03:08 AM, tien.fong.chee@intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Adding some details about size in bytes to each section.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>  arch/arm/mach-socfpga/include/mach/boot0.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 

Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>

Dinh

Patch

diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h b/arch/arm/mach-socfpga/include/mach/boot0.h
index 22d9e7f..e06b548 100644
--- a/arch/arm/mach-socfpga/include/mach/boot0.h
+++ b/arch/arm/mach-socfpga/include/mach/boot0.h
@@ -11,8 +11,8 @@ 
 	.balignl 64,0xf33db33f;
 
 	.word	0x1337c0d3;	/* SoCFPGA preloader validation word */
-	.word	0xc01df00d;	/* Version, flags, length */
-	.word	0xcafec0d3;	/* Checksum, zero-pad */
+	.word	0xc01df00d;	/* Header length(2B),flags(1B),version(1B) */
+	.word	0xcafec0d3;	/* Simple checksum(2B),spare offset(2B) */
 	nop;
 
 	b reset;		/* SoCFPGA jumps here */