From patchwork Fri Oct 13 08:08:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 825266 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yD0x55gVNz9sPm for ; Fri, 13 Oct 2017 19:19:05 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 83308C21F95; Fri, 13 Oct 2017 08:14:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 1FBDFC21F53; Fri, 13 Oct 2017 08:11:37 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4FD95C21FB4; Fri, 13 Oct 2017 08:10:35 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lists.denx.de (Postfix) with ESMTPS id 76F54C21F61 for ; Fri, 13 Oct 2017 08:10:28 +0000 (UTC) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Oct 2017 01:10:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.43,369,1503385200"; d="scan'208";a="146037069" Received: from tfchee-mobl.gar.corp.intel.com (HELO tienfong.fm.intel.com, ) ([10.226.242.149]) by orsmga002.jf.intel.com with ESMTP; 13 Oct 2017 01:10:00 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Fri, 13 Oct 2017 16:08:56 +0800 Message-Id: <1507882137-27841-20-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507882137-27841-1-git-send-email-tien.fong.chee@intel.com> References: <1507882137-27841-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut , Tien Fong Chee , Ching Liang See , Tien Fong , Westergteen Dalon Subject: [U-Boot] [PATCH v3 19/20] arm: socfpga: Enable DDR working X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee SPL configures DDR by programming peripheral raw binary file and calibrating DDR. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/spl.c | 56 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index aba116d..6c9bf81 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -22,6 +23,10 @@ #include #include #include +#include +#include +#include +#include #include #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #include @@ -29,6 +34,9 @@ DECLARE_GLOBAL_DATA_PTR; +#define BSIZE 4096 +#define PERIPH_RBF 0 + #if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; @@ -197,6 +205,12 @@ void board_init_f(ulong dummy) #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) void spl_board_init(void) { + int rval = 0; + int len = 0; + u32 buffer[BSIZE] __aligned(ARCH_DMA_MINALIGN); + struct spl_boot_device bootdev; + fpga_fs_info fpga_fsinfo; + /* configuring the clock based on handoff */ cm_basic_init(gd->fdt_blob); WATCHDOG_RESET(); @@ -214,6 +228,48 @@ void spl_board_init(void) /* Add device descriptor to FPGA device table */ socfpga_fpga_add(); + + bootdev.boot_device = spl_boot_device(); + + if (BOOT_DEVICE_MMC1 == bootdev.boot_device) { + struct mmc *mmc = NULL; + int err = 0; + + spl_mmc_find_device(&mmc, bootdev.boot_device); + + err = mmc_init(mmc); + + if (err) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + printf("spl: mmc init failed with error: %d\n", err); +#endif + return; + } + + fpga_fsinfo.interface = "mmc"; + fpga_fsinfo.fstype = FS_TYPE_FAT; + } + + fpga_fsinfo.dev_part = (char *)get_cff_devpart(gd->fdt_blob, + &len); + + fpga_fsinfo.filename = (char *)get_cff_filename(gd->fdt_blob, + &len, + PERIPH_RBF); + + /* Program peripheral RBF */ + if (fpga_fsinfo.filename) + rval = fpga_fsload(0, buffer, BSIZE, &fpga_fsinfo); + else { + printf("Failed to find peripheral RBF file from DTS\n"); + return; + } + + if (!rval) { + config_pins(gd->fdt_blob, "shared"); + + ddr_calibration_sequence(); + } } void board_init_f(ulong dummy)