[U-Boot,v3,19/20] arm: socfpga: Enable DDR working

Message ID 1507882137-27841-20-git-send-email-tien.fong.chee@intel.com
State New
Delegated to: Marek Vasut
Headers show
Series
  • Add FPGA, SDRAM, SPL loadfs U-boot & booting to console
Related show

Commit Message

Chee, Tien Fong Oct. 13, 2017, 8:08 a.m.
From: Tien Fong Chee <tien.fong.chee@intel.com>

SPL configures DDR by programming peripheral raw binary file
and calibrating DDR.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/spl.c | 56 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)

Patch

diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index aba116d..6c9bf81 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -15,6 +15,7 @@ 
 #include <asm/arch/system_manager.h>
 #include <asm/arch/freeze_controller.h>
 #include <asm/arch/clock_manager.h>
+#include <asm/arch/fpga_manager.h>
 #include <asm/arch/misc.h>
 #include <asm/arch/scan_manager.h>
 #include <asm/arch/sdram.h>
@@ -22,6 +23,10 @@ 
 #include <asm/arch/nic301.h>
 #include <asm/sections.h>
 #include <fdtdec.h>
+#include <fat.h>
+#include <fs.h>
+#include <linux/ctype.h>
+#include <mmc.h>
 #include <watchdog.h>
 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 #include <asm/arch/pinmux.h>
@@ -29,6 +34,9 @@ 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define BSIZE	4096
+#define PERIPH_RBF	0
+
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
 	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
@@ -197,6 +205,12 @@  void board_init_f(ulong dummy)
 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 void spl_board_init(void)
 {
+	int rval = 0;
+	int len = 0;
+	u32 buffer[BSIZE] __aligned(ARCH_DMA_MINALIGN);
+	struct spl_boot_device bootdev;
+	fpga_fs_info fpga_fsinfo;
+
 	/* configuring the clock based on handoff */
 	cm_basic_init(gd->fdt_blob);
 	WATCHDOG_RESET();
@@ -214,6 +228,48 @@  void spl_board_init(void)
 
 	/* Add device descriptor to FPGA device table */
 	socfpga_fpga_add();
+
+	bootdev.boot_device = spl_boot_device();
+
+	if (BOOT_DEVICE_MMC1 == bootdev.boot_device) {
+		struct mmc *mmc = NULL;
+		int err = 0;
+
+		spl_mmc_find_device(&mmc, bootdev.boot_device);
+
+		err = mmc_init(mmc);
+
+		if (err) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+			printf("spl: mmc init failed with error: %d\n", err);
+#endif
+			return;
+		}
+
+		fpga_fsinfo.interface = "mmc";
+		fpga_fsinfo.fstype = FS_TYPE_FAT;
+	}
+
+	fpga_fsinfo.dev_part = (char *)get_cff_devpart(gd->fdt_blob,
+							&len);
+
+	fpga_fsinfo.filename = (char *)get_cff_filename(gd->fdt_blob,
+							 &len,
+							 PERIPH_RBF);
+
+	/* Program peripheral RBF */
+	if (fpga_fsinfo.filename)
+		rval = fpga_fsload(0, buffer, BSIZE, &fpga_fsinfo);
+	else {
+		printf("Failed to find peripheral RBF file from DTS\n");
+		return;
+	}
+
+	if (!rval) {
+		config_pins(gd->fdt_blob, "shared");
+
+		ddr_calibration_sequence();
+	}
 }
 
 void board_init_f(ulong dummy)