[U-Boot,v3,11/20] arm: socfpga: Add DDR driver for Arria 10

Message ID 1507882137-27841-12-git-send-email-tien.fong.chee@intel.com
State Superseded
Delegated to: Marek Vasut
Headers show
Series
  • Add FPGA, SDRAM, SPL loadfs U-boot & booting to console
Related show

Commit Message

Chee, Tien Fong Oct. 13, 2017, 8:08 a.m.
From: Tien Fong Chee <tien.fong.chee@intel.com>

Add DDR driver suppport for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/include/mach/sdram.h         |   2 +
 arch/arm/mach-socfpga/include/mach/sdram_arria10.h |   2 +
 drivers/ddr/altera/Makefile                        |   1 +
 drivers/ddr/altera/sdram_arria10.c                 | 736 +++++++++++++++++++++
 4 files changed, 741 insertions(+)
 create mode 100644 drivers/ddr/altera/sdram_arria10.c

Comments

Dinh Nguyen Oct. 17, 2017, 3:08 a.m. | #1
On 10/13/2017 03:08 AM, tien.fong.chee@intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Add DDR driver suppport for Arria 10.

s/suppport/support

> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>  arch/arm/mach-socfpga/include/mach/sdram.h         |   2 +
>  arch/arm/mach-socfpga/include/mach/sdram_arria10.h |   2 +
>  drivers/ddr/altera/Makefile                        |   1 +
>  drivers/ddr/altera/sdram_arria10.c                 | 736 +++++++++++++++++++++
>  4 files changed, 741 insertions(+)
>  create mode 100644 drivers/ddr/altera/sdram_arria10.c
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
> index 137e073..33f830b 100644
> --- a/arch/arm/mach-socfpga/include/mach/sdram.h
> +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
> @@ -10,6 +10,8 @@
>  
>  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  #include <asm/arch/sdram_gen5.h>
> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#include <asm/arch/sdram_arria10.h>
>  #endif
>  
>  #endif
> diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> index 1d7b7c1..e7a2503 100644
> --- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> +++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> @@ -8,6 +8,7 @@
>  #define _SOCFPGA_SDRAM_ARRIA10_H_
>  
>  #ifndef __ASSEMBLY__
> +int ddr_calibration_sequence(void);
>  
>  struct socfpga_ecc_hmc {
>  	u32 ip_rev_id;
> @@ -204,6 +205,7 @@ struct socfpga_io48_mmr {
>  	u32 niosreserve1;
>  	u32 niosreserve2;
>  };
> +
>  #endif /*__ASSEMBLY__*/
>  
>  #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK		0x1F000000
> diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
> index ac4ab85..02f8b7c 100644
> --- a/drivers/ddr/altera/Makefile
> +++ b/drivers/ddr/altera/Makefile
> @@ -10,4 +10,5 @@
>  
>  ifdef CONFIG_ALTERA_SDRAM
>  obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
> +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
>  endif
> diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c
> new file mode 100644
> index 0000000..be8aff3
> --- /dev/null
> +++ b/drivers/ddr/altera/sdram_arria10.c
> @@ -0,0 +1,736 @@
> +/*
> + * Copyright (C) 2017 Intel Corporation <www.intel.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0
> + */
> +
> +#include <common.h>
> +#include <errno.h>
> +#include <fdtdec.h>
> +#include <malloc.h>
> +#include <wait_bit.h>
> +#include <watchdog.h>
> +#include <asm/io.h>
> +#include <asm/arch/fpga_manager.h>
> +#include <asm/arch/misc.h>
> +#include <asm/arch/reset_manager.h>
> +#include <asm/arch/sdram.h>
> +#include <linux/kernel.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static void sdram_mmr_init(void);
> +static unsigned long long sdram_size_calc(void);

Use uint64_t

> +
> +/* FAWBANK - Number of Bank of a given device involved in the FAW period. */
> +#define ARRIA10_SDR_ACTIVATE_FAWBANK	(0x1)
> +
> +#define ARRIA_DDR_CONFIG(A, B, C, R) \
> +	(((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
> +#define DDR_CONFIG_ELEMENTS	ARRAY_SIZE(ddr_config)
> +#define DDR_REG_SEQ2CORE        0xFFD0507C
> +#define DDR_REG_CORE2SEQ        0xFFD05078
> +#define DDR_READ_LATENCY_DELAY	40
> +#define DDR_SIZE_2GB_HEX	0x80000000
> +#define DDR_MAX_TRIES		0x00100000
> +
> +#define IO48_MMR_DRAMSTS	0xFFCFA0EC
> +#define IO48_MMR_NIOS2_RESERVE0	0xFFCFA110
> +#define IO48_MMR_NIOS2_RESERVE1	0xFFCFA114
> +#define IO48_MMR_NIOS2_RESERVE2	0xFFCFA118
> +
> +#define SEQ2CORE_MASK		0xF
> +#define CORE2SEQ_INT_REQ	0xF
> +#define SEQ2CORE_INT_RESP_BIT	3
> +
> +static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
> +		(void *)SOCFPGA_SDR_ADDRESS;
> +static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
> +		(void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
> +static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
> +		*socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
> +		(void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
> +static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
> +		(void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
> +static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
> +		(void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
> +
> +/* The followring are the supported configurations */

s/followring/following

> +static u32 ddr_config[] = {
> +	/* Chip - Row - Bank - Column Style */
> +	/* All Types */
> +	ARRIA_DDR_CONFIG(0, 3, 10, 12),
> +	ARRIA_DDR_CONFIG(0, 3, 10, 13),
> +	ARRIA_DDR_CONFIG(0, 3, 10, 14),
> +	ARRIA_DDR_CONFIG(0, 3, 10, 15),
> +	ARRIA_DDR_CONFIG(0, 3, 10, 16),
> +	ARRIA_DDR_CONFIG(0, 3, 10, 17),
> +	/* LPDDR x16 */
> +	ARRIA_DDR_CONFIG(0, 3, 11, 14),
> +	ARRIA_DDR_CONFIG(0, 3, 11, 15),
> +	ARRIA_DDR_CONFIG(0, 3, 11, 16),
> +	ARRIA_DDR_CONFIG(0, 3, 12, 15),
> +	/* DDR4 Only */
> +	ARRIA_DDR_CONFIG(0, 4, 10, 14),
> +	ARRIA_DDR_CONFIG(0, 4, 10, 15),
> +	ARRIA_DDR_CONFIG(0, 4, 10, 16),
> +	ARRIA_DDR_CONFIG(0, 4, 10, 17),	/* 14 */
> +	/* Chip - Bank - Row - Column Style */
> +	ARRIA_DDR_CONFIG(1, 3, 10, 12),
> +	ARRIA_DDR_CONFIG(1, 3, 10, 13),
> +	ARRIA_DDR_CONFIG(1, 3, 10, 14),
> +	ARRIA_DDR_CONFIG(1, 3, 10, 15),
> +	ARRIA_DDR_CONFIG(1, 3, 10, 16),
> +	ARRIA_DDR_CONFIG(1, 3, 10, 17),
> +	ARRIA_DDR_CONFIG(1, 3, 11, 14),
> +	ARRIA_DDR_CONFIG(1, 3, 11, 15),
> +	ARRIA_DDR_CONFIG(1, 3, 11, 16),
> +	ARRIA_DDR_CONFIG(1, 3, 12, 15),
> +	/* DDR4 Only */
> +	ARRIA_DDR_CONFIG(1, 4, 10, 14),
> +	ARRIA_DDR_CONFIG(1, 4, 10, 15),
> +	ARRIA_DDR_CONFIG(1, 4, 10, 16),
> +	ARRIA_DDR_CONFIG(1, 4, 10, 17),
> +};
> +
> +static int match_ddr_conf(u32 ddr_conf)
> +{
> +	int i;
> +/
> +	for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
> +		if (ddr_conf == ddr_config[i])
> +			return i;
> +	}
> +	return 0;
> +}
> +
> +/* Check whether SDRAM is successfully Calibrated */
> +static int is_sdram_cal_success(void)
> +{
> +	return readl(&socfpga_ecc_hmc_base->ddrcalstat);
> +}
> +
> +static unsigned char ddr_get_bit(u32 ereg, unsigned char bit)
> +{
> +	u32 reg = readl(ereg);
> +
> +	return (reg & BIT(bit)) ? 1 : 0;
> +}
> +
> +static unsigned char ddr_wait_bit(u32 ereg, u32 bit,
> +			   u32 expected, u32 timeout_usec)
> +{
> +	u32 tmr;
> +
> +	for (tmr = 0; tmr < timeout_usec; tmr += 100) {
> +		udelay(100);
> +		WATCHDOG_RESET();
> +		if (ddr_get_bit(ereg, bit) == expected)
> +			return 0;
> +	}
> +
> +	return 1;
> +}
> +
> +static void ddr_delay(u32 delay)
> +{
> +	int tmr;
> +
> +	for (tmr = 0; tmr < delay; tmr++) {
> +		mdelay(1);
> +		WATCHDOG_RESET();
> +	}
> +}
> +
> +static int emif_clear(void)
> +{
> +	u32 i = DDR_MAX_TRIES;
> +	u8 ret = 0;
> +
> +	writel(0, DDR_REG_CORE2SEQ);
> +
> +	do {
> +		ret = !wait_for_bit(__func__, (u32 *)DDR_REG_SEQ2CORE,
> +				   SEQ2CORE_MASK, 1, 50, 0);
> +	} while (ret && (--i > 0));
> +
> +	return !i;
> +}
> +
> +static int emif_reset(void)
> +{
> +	u32 c2s, s2c;
> +
> +	c2s = readl(DDR_REG_CORE2SEQ);
> +	s2c = readl(DDR_REG_SEQ2CORE);
> +
> +	debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
> +	     c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
> +	     readl(IO48_MMR_NIOS2_RESERVE1),
> +	     readl(IO48_MMR_NIOS2_RESERVE2),
> +	     readl(IO48_MMR_DRAMSTS));
> +
> +	if ((s2c & SEQ2CORE_MASK) && emif_clear()) {
> +		printf("failed emif_clear()\n");
> +		return -EPERM;
> +	}
> +
> +	writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
> +
> +	if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) {
> +		printf("emif_reset failed to see interrupt acknowledge\n");
> +		return -EPERM;
> +	} else {
> +		printf("emif_reset interrupt acknowledged\n");
> +	}
> +
> +	if (emif_clear()) {
> +		printf("emif_clear() failed\n");

Use debug() instead of all the printf()'s.

> +		return -EPERM;
> +	}
> +	debug("emif_reset interrupt cleared\n");
> +
> +	debug("nr0=%08x nr1=%08x nr2=%08x\n",
> +	     readl(IO48_MMR_NIOS2_RESERVE0),
> +	     readl(IO48_MMR_NIOS2_RESERVE1),
> +	     readl(IO48_MMR_NIOS2_RESERVE2));
> +
> +	return 0;

emif_reset() has all these return values, but the actual call to
emif_reset() is not checking the values at all.

> +}
> +
> +static int ddr_setup(void)
> +{
> +	int i, j, ddr_setup_complete = 0;
> +
> +	/* Try 3 times to do a calibration */
> +	for (i = 0; (i < 3) && !ddr_setup_complete; i++) {
> +		WATCHDOG_RESET();
> +
> +		/* A delay to wait for calibration bit to set */
> +		for (j = 0; (j < 10) && !ddr_setup_complete; j++) {
> +			ddr_delay(500);

Looks like all ddr_delay() is doing is call to 1ms delay, and the max
delay is 5s. Looks like you can rid of the ddr_delay() function and do
the wait here.

> +			ddr_setup_complete = is_sdram_cal_success();
> +		}
> +
> +		if (!ddr_setup_complete)
> +			emif_reset();
> +	}
> +
> +	if (!ddr_setup_complete) {
> +		puts("Error: Could Not Calibrate SDRAM\n");
> +		return -EPERM;
> +	}

Move this block of code up to where you did the check for
!ddr_setup_complete the first time.

> +
> +	return 0;
> +}
> +
> +/* Function to startup the SDRAM*/
> +static int sdram_startup(void)
> +{
> +	/* Release NOC ddr scheduler from reset */
> +	socfpga_reset_deassert_noc_ddr_scheduler();
> +
> +	/* Bringup the DDR (calibration and configuration) */
> +	return ddr_setup();
> +}
> +
> +static unsigned long long sdram_size_calc(void)

Use uint64_t

> +{
> +	u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
> +
> +	unsigned long long size = BIT(((dramaddrw &

uint64_t

> +		IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK) >>
> +		IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT) +
> +		((dramaddrw &
> +		IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
> +		IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT) +
> +		((dramaddrw &
> +		IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
> +		IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
> +		((dramaddrw &
> +		IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
> +		IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT) +
> +		(dramaddrw & IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK));
> +
> +	size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
> +		       ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));

Should add a debug statement here for the size.

> +
> +	return size;
> +}
> +
> +/* Function to initialize SDRAM MMR and NOC DDR scheduler*/
> +static void sdram_mmr_init(void)
> +{
> +	u32 update_value, io48_value;
> +	u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0);
> +	u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1);
> +	u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
> +	u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0);
> +	u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1);
> +	u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2);
> +	u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3);
> +	u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4);
> +	u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9);
> +	u32 ddrioctl;
> +
> +	/*
> +	 * Configure the DDR IO size [0xFFCFB008]
> +	 * niosreserve0: Used to indicate DDR width &
> +	 *	bit[7:0] = Number of data bits (0x20 for 32bit)
> +	 *	bit[8]   = 1 if user-mode OCT is present
> +	 *	bit[9]   = 1 if warm reset compiled into EMIF Cal Code
> +	 *	bit[10]  = 1 if warm reset is on during generation in EMIF Cal
> +	 * niosreserve1: IP ADCDS version encoded as 16 bit value
> +	 *	bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
> +	 *			    3=EAP, 4-6 are reserved)
> +	 *	bit[5:3] = Service Pack # (e.g. 1)
> +	 *	bit[9:6] = Minor Release #
> +	 *	bit[14:10] = Major Release #
> +	 */
> +	if ((socfpga_io48_mmr_base->niosreserve1 >> 6) & 0x1FF) {
> +		update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
> +		writel(((update_value & 0xFF) >> 5),
> +		       &socfpga_ecc_hmc_base->ddrioctrl);
> +	}
> +
> +	ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);
> +
> +	/* Set the DDR Configuration [0xFFD12400] */
> +	io48_value = ARRIA_DDR_CONFIG(
> +			((ctrlcfg1 &
> +			IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK) >>
> +			IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT),
> +			((dramaddrw &
> +			IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
> +			IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
> +			((dramaddrw &
> +			IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
> +			IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT),
> +			(dramaddrw &
> +			IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK),
> +			((dramaddrw &
> +			IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
> +			IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT));
> +
> +	update_value = match_ddr_conf(io48_value);
> +	if (update_value)
> +		writel(update_value,
> +		&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf);
> +
> +	/*
> +	 * Configure DDR timing [0xFFD1240C]
> +	 *  RDTOMISS = tRTP + tRP + tRCD - BL/2
> +	 *  WRTOMISS = WL + tWR + tRP + tRCD and
> +	 *    WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns  so...
> +	 *  First part of equation is in memory clock units so divide by 2
> +	 *  for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
> +	 *  WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
> +	 */
> +	u32 ctrlcfg0_cfg_ctrl_burst_len =
> +		(ctrlcfg0 & IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK) >>
> +		IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT;
> +
> +	u32 caltim0_cfg_act_to_rdwr = caltim0 &
> +		IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK;
> +
> +	u32 caltim0_cfg_act_to_act =
> +		(caltim0 & IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK) >>
> +		IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT;
> +
> +	u32 caltim0_cfg_act_to_act_db =
> +		(caltim0 &
> +		IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK) >>
> +		IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT;
> +
> +	u32 caltim1_cfg_rd_to_wr =
> +		(caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK) >>
> +		IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT;
> +
> +	u32 caltim1_cfg_rd_to_rd_dc =
> +		(caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK) >>
> +		IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT;
> +
> +	u32 caltim1_cfg_rd_to_wr_dc =
> +		(caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK) >>
> +		IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT;
> +
> +	u32 caltim2_cfg_rd_to_pch =
> +		(caltim2 & IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK) >>
> +		IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT;
> +
> +	u32 caltim3_cfg_wr_to_rd =
> +		(caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK) >>
> +		IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT;
> +
> +	u32 caltim3_cfg_wr_to_rd_dc =
> +		(caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK) >>
> +		IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT;
> +
> +	u32 caltim4_cfg_pch_to_valid =
> +		(caltim4 & IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK) >>
> +		IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT;
> +
> +	u32 caltim9_cfg_4_act_to_act = caltim9 &
> +		IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK;
> +
> +	update_value = (caltim2_cfg_rd_to_pch +  caltim4_cfg_pch_to_valid +
> +			caltim0_cfg_act_to_rdwr -
> +			(ctrlcfg0_cfg_ctrl_burst_len >> 2));
> +
> +	io48_value = ((((socfpga_io48_mmr_base->dramtiming0 &
> +		      ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +
> +		      (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
> +		      /* Up to here was in memory cycles so divide by 2 */
> +		      caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr +
> +		      caltim4_cfg_pch_to_valid);
> +
> +	writel(((caltim0_cfg_act_to_act <<
> +			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) |
> +		(update_value <<
> +			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) |
> +		(io48_value <<
> +			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) |
> +		((ctrlcfg0_cfg_ctrl_burst_len >> 2) <<
> +			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) |
> +		(caltim1_cfg_rd_to_wr <<
> +			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) |
> +		(caltim3_cfg_wr_to_rd <<
> +			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) |
> +		(((ddrioctl == 1) ? 1 : 0) <<
> +			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)),
> +		&socfpga_noc_ddr_scheduler_base->
> +			ddr_t_main_scheduler_ddrtiming);
> +
> +	/* Configure DDR mode [0xFFD12410] [precharge = 0] */
> +	writel(((ddrioctl ? 0 : 1) <<
> +		ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB),
> +		&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);
> +
> +	/* Configure the read latency [0xFFD12414] */
> +	writel(((socfpga_io48_mmr_base->dramtiming0 &
> +		ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +
> +		DDR_READ_LATENCY_DELAY,
> +		&socfpga_noc_ddr_scheduler_base->
> +			ddr_t_main_scheduler_readlatency);
> +
> +	/*
> +	 * Configuring timing values concerning activate commands
> +	 * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR]
> +	 */
> +	writel(((caltim0_cfg_act_to_act_db <<
> +			ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) |
> +		(caltim9_cfg_4_act_to_act <<
> +			ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) |
> +		(ARRIA10_SDR_ACTIVATE_FAWBANK <<
> +			ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)),
> +		&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate);
> +
> +	/*
> +	 * Configuring timing values concerning device to device data bus
> +	 * ownership change [0xFFD1243C]
> +	 */
> +	writel(((caltim1_cfg_rd_to_rd_dc <<
> +			ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) |
> +		(caltim1_cfg_rd_to_wr_dc <<
> +			ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) |
> +		(caltim3_cfg_wr_to_rd_dc <<
> +			ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)),
> +		&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev);
> +
> +	/* Enable or disable the SDRAM ECC */
> +	if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) {
> +		setbits_le32(&socfpga_ecc_hmc_base->eccctrl,
> +			     (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
> +			      ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
> +			      ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
> +		clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
> +			     (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
> +			      ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK));
> +		setbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
> +			     (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
> +			      ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
> +	} else {
> +		clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
> +			     (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
> +			      ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
> +			      ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
> +		clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
> +			     (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
> +			      ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
> +	}
> +}
> +
> +struct firewall_entry {
> +	const char *prop_name;
> +	const u32 cfg_addr;
> +	const u32 en_addr;
> +	const u32 en_bit;
> +};
> +#define FW_MPU_FPGA_ADDRESS \
> +	((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\
> +	SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)
> +
> +#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(ADDR) \
> +		(SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + \
> +		offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram, ADDR))
> +
> +#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(ADDR) \
> +		(SOCFPGA_SDR_FIREWALL_L3_ADDRESS + \
> +		offsetof(struct socfpga_noc_fw_ddr_l3, ADDR))
> +
> +const struct firewall_entry firewall_table[] = {
> +	{
> +		"altr,mpu0",
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion0addr),
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
> +		ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK
> +	},
> +	{
> +		"altr,mpu1",
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion1addr),
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
> +		ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK
> +	},
> +	{
> +		"altr,mpu2",
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion2addr),
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
> +		ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK
> +	},
> +	{
> +		"altr,mpu3",
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion3addr),
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
> +		ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK
> +	},
> +	{
> +		"altr,l3-0",
> +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion0addr),
> +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
> +		ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK
> +	},
> +	{
> +		"altr,l3-1",
> +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion1addr),
> +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
> +		ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK
> +	},
> +	{
> +		"altr,l3-2",
> +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion2addr),
> +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
> +		ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK
> +	},
> +	{
> +		"altr,l3-3",
> +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion3addr),
> +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
> +		ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK
> +	},
> +	{
> +		"altr,l3-4",
> +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion4addr),
> +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
> +		ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK
> +	},
> +	{
> +		"altr,l3-5",
> +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion5addr),
> +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
> +		ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK
> +	},
> +	{
> +		"altr,l3-6",
> +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion6addr),
> +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
> +		ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK
> +	},
> +	{
> +		"altr,l3-7",
> +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion7addr),
> +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
> +		ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK
> +	},
> +	{
> +		"altr,fpga2sdram0-0",
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
> +		(fpga2sdram0region0addr),
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
> +		ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK
> +	},
> +	{
> +		"altr,fpga2sdram0-1",
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
> +		(fpga2sdram0region1addr),
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
> +		ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK
> +	},
> +	{
> +		"altr,fpga2sdram0-2",
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
> +		(fpga2sdram0region2addr),
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
> +		ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK
> +	},
> +	{
> +		"altr,fpga2sdram0-3",
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
> +		(fpga2sdram0region3addr),
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
> +		ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK
> +	},
> +	{
> +		"altr,fpga2sdram1-0",
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
> +		(fpga2sdram1region0addr),
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
> +		ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK
> +	},
> +	{
> +		"altr,fpga2sdram1-1",
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
> +		(fpga2sdram1region1addr),
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
> +		ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK
> +	},
> +	{
> +		"altr,fpga2sdram1-2",
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
> +		(fpga2sdram1region2addr),
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
> +		ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK
> +	},
> +	{
> +		"altr,fpga2sdram1-3",
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
> +		(fpga2sdram1region3addr),
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
> +		ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK
> +	},
> +	{
> +		"altr,fpga2sdram2-0",
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
> +		(fpga2sdram2region0addr),
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
> +		ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK
> +	},
> +	{
> +		"altr,fpga2sdram2-1",
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
> +		(fpga2sdram2region1addr),
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
> +		ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK
> +	},
> +	{
> +		"altr,fpga2sdram2-2",
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
> +		(fpga2sdram2region2addr),
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
> +		ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK
> +	},
> +	{
> +		"altr,fpga2sdram2-3",
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
> +		(fpga2sdram2region3addr),
> +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
> +		ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK
> +	},
> +
> +};
> +
> +static int of_sdram_firewall_setup(const void *blob)
> +{
> +	int child, i, node;
> +	u32 start_end[2];
> +
> +	node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC);
> +	if (node < 0)
> +		return -ENXIO;
> +
> +	child = fdt_first_subnode(blob, node);
> +	if (child < 0)
> +		return -ENXIO;
> +
> +	/* set to default state */
> +	writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);
> +	writel(0, &socfpga_noc_fw_ddr_l3_base->enable);
> +
> +
> +	for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {
> +		if (!fdtdec_get_int_array(blob, child,
> +					  firewall_table[i].prop_name,
> +					  start_end, 2)) {
> +			writel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) |
> +				(start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB),
> +				 firewall_table[i].cfg_addr);
> +			setbits_le32(firewall_table[i].en_addr,
> +				     firewall_table[i].en_bit);
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +int ddr_calibration_sequence(void)
> +{
> +	WATCHDOG_RESET();
> +
> +	/* Check to see if SDRAM cal was success */
> +	if (sdram_startup()) {
> +		puts("DDRCAL: Failed\n");
> +		return -EPERM;
> +	}
> +
> +	puts("DDRCAL: Success\n");
> +
> +	WATCHDOG_RESET();
> +
> +	/* initialize the MMR register */
> +	sdram_mmr_init();
> +
> +	/* assigning the SDRAM size */
> +	unsigned long long size = sdram_size_calc();
> +
> +	/* If a weird value, use default Config size */
> +	/* Up to 2GB is supported, 2GB would be used if more than that */

Fix comment style.

> +	if (size <= 0)

Can size ever be less than zero?

Dinh
Chee, Tien Fong Oct. 23, 2017, 7:45 a.m. | #2
On Isn, 2017-10-16 at 22:08 -0500, Dinh Nguyen wrote:
> 

> On 10/13/2017 03:08 AM, tien.fong.chee@intel.com wrote:

> > 

> > From: Tien Fong Chee <tien.fong.chee@intel.com>

> > 

> > Add DDR driver suppport for Arria 10.

> s/suppport/support

> 

Okay.
> > 

> > 

> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>

> > ---

> >  arch/arm/mach-socfpga/include/mach/sdram.h         |   2 +

> >  arch/arm/mach-socfpga/include/mach/sdram_arria10.h |   2 +

> >  drivers/ddr/altera/Makefile                        |   1 +

> >  drivers/ddr/altera/sdram_arria10.c                 | 736

> > +++++++++++++++++++++

> >  4 files changed, 741 insertions(+)

> >  create mode 100644 drivers/ddr/altera/sdram_arria10.c

> > 

> > diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h

> > b/arch/arm/mach-socfpga/include/mach/sdram.h

> > index 137e073..33f830b 100644

> > --- a/arch/arm/mach-socfpga/include/mach/sdram.h

> > +++ b/arch/arm/mach-socfpga/include/mach/sdram.h

> > @@ -10,6 +10,8 @@

> >  

> >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)

> >  #include <asm/arch/sdram_gen5.h>

> > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)

> > +#include <asm/arch/sdram_arria10.h>

> >  #endif

> >  

> >  #endif

> > diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h

> > b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h

> > index 1d7b7c1..e7a2503 100644

> > --- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h

> > +++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h

> > @@ -8,6 +8,7 @@

> >  #define _SOCFPGA_SDRAM_ARRIA10_H_

> >  

> >  #ifndef __ASSEMBLY__

> > +int ddr_calibration_sequence(void);

> >  

> >  struct socfpga_ecc_hmc {

> >  	u32 ip_rev_id;

> > @@ -204,6 +205,7 @@ struct socfpga_io48_mmr {

> >  	u32 niosreserve1;

> >  	u32 niosreserve2;

> >  };

> > +

> >  #endif /*__ASSEMBLY__*/

> >  

> >  #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK		0x1

> > F000000

> > diff --git a/drivers/ddr/altera/Makefile

> > b/drivers/ddr/altera/Makefile

> > index ac4ab85..02f8b7c 100644

> > --- a/drivers/ddr/altera/Makefile

> > +++ b/drivers/ddr/altera/Makefile

> > @@ -10,4 +10,5 @@

> >  

> >  ifdef CONFIG_ALTERA_SDRAM

> >  obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o

> > +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o

> >  endif

> > diff --git a/drivers/ddr/altera/sdram_arria10.c

> > b/drivers/ddr/altera/sdram_arria10.c

> > new file mode 100644

> > index 0000000..be8aff3

> > --- /dev/null

> > +++ b/drivers/ddr/altera/sdram_arria10.c

> > @@ -0,0 +1,736 @@

> > +/*

> > + * Copyright (C) 2017 Intel Corporation <www.intel.com>

> > + *

> > + * SPDX-License-Identifier:    GPL-2.0

> > + */

> > +

> > +#include <common.h>

> > +#include <errno.h>

> > +#include <fdtdec.h>

> > +#include <malloc.h>

> > +#include <wait_bit.h>

> > +#include <watchdog.h>

> > +#include <asm/io.h>

> > +#include <asm/arch/fpga_manager.h>

> > +#include <asm/arch/misc.h>

> > +#include <asm/arch/reset_manager.h>

> > +#include <asm/arch/sdram.h>

> > +#include <linux/kernel.h>

> > +

> > +DECLARE_GLOBAL_DATA_PTR;

> > +

> > +static void sdram_mmr_init(void);

> > +static unsigned long long sdram_size_calc(void);

> Use uint64_t

> 

Okay.
> > 

> > +

> > +/* FAWBANK - Number of Bank of a given device involved in the FAW

> > period. */

> > +#define ARRIA10_SDR_ACTIVATE_FAWBANK	(0x1)

> > +

> > +#define ARRIA_DDR_CONFIG(A, B, C, R) \

> > +	(((A) << 24) | ((B) << 16) | ((C) << 8) | (R))

> > +#define DDR_CONFIG_ELEMENTS	ARRAY_SIZE(ddr_config)

> > +#define DDR_REG_SEQ2CORE        0xFFD0507C

> > +#define DDR_REG_CORE2SEQ        0xFFD05078

> > +#define DDR_READ_LATENCY_DELAY	40

> > +#define DDR_SIZE_2GB_HEX	0x80000000

> > +#define DDR_MAX_TRIES		0x00100000

> > +

> > +#define IO48_MMR_DRAMSTS	0xFFCFA0EC

> > +#define IO48_MMR_NIOS2_RESERVE0	0xFFCFA110

> > +#define IO48_MMR_NIOS2_RESERVE1	0xFFCFA114

> > +#define IO48_MMR_NIOS2_RESERVE2	0xFFCFA118

> > +

> > +#define SEQ2CORE_MASK		0xF

> > +#define CORE2SEQ_INT_REQ	0xF

> > +#define SEQ2CORE_INT_RESP_BIT	3

> > +

> > +static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =

> > +		(void *)SOCFPGA_SDR_ADDRESS;

> > +static const struct socfpga_noc_ddr_scheduler

> > *socfpga_noc_ddr_scheduler_base =

> > +		(void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;

> > +static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram

> > +		*socfpga_noc_fw_ddr_mpu_fpga2sdram_base =

> > +		(void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;

> > +static const struct socfpga_noc_fw_ddr_l3

> > *socfpga_noc_fw_ddr_l3_base =

> > +		(void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;

> > +static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =

> > +		(void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;

> > +

> > +/* The followring are the supported configurations */

> s/followring/following

> 

Okay.
> > 

> > +static u32 ddr_config[] = {

> > +	/* Chip - Row - Bank - Column Style */

> > +	/* All Types */

> > +	ARRIA_DDR_CONFIG(0, 3, 10, 12),

> > +	ARRIA_DDR_CONFIG(0, 3, 10, 13),

> > +	ARRIA_DDR_CONFIG(0, 3, 10, 14),

> > +	ARRIA_DDR_CONFIG(0, 3, 10, 15),

> > +	ARRIA_DDR_CONFIG(0, 3, 10, 16),

> > +	ARRIA_DDR_CONFIG(0, 3, 10, 17),

> > +	/* LPDDR x16 */

> > +	ARRIA_DDR_CONFIG(0, 3, 11, 14),

> > +	ARRIA_DDR_CONFIG(0, 3, 11, 15),

> > +	ARRIA_DDR_CONFIG(0, 3, 11, 16),

> > +	ARRIA_DDR_CONFIG(0, 3, 12, 15),

> > +	/* DDR4 Only */

> > +	ARRIA_DDR_CONFIG(0, 4, 10, 14),

> > +	ARRIA_DDR_CONFIG(0, 4, 10, 15),

> > +	ARRIA_DDR_CONFIG(0, 4, 10, 16),

> > +	ARRIA_DDR_CONFIG(0, 4, 10, 17),	/* 14 */

> > +	/* Chip - Bank - Row - Column Style */

> > +	ARRIA_DDR_CONFIG(1, 3, 10, 12),

> > +	ARRIA_DDR_CONFIG(1, 3, 10, 13),

> > +	ARRIA_DDR_CONFIG(1, 3, 10, 14),

> > +	ARRIA_DDR_CONFIG(1, 3, 10, 15),

> > +	ARRIA_DDR_CONFIG(1, 3, 10, 16),

> > +	ARRIA_DDR_CONFIG(1, 3, 10, 17),

> > +	ARRIA_DDR_CONFIG(1, 3, 11, 14),

> > +	ARRIA_DDR_CONFIG(1, 3, 11, 15),

> > +	ARRIA_DDR_CONFIG(1, 3, 11, 16),

> > +	ARRIA_DDR_CONFIG(1, 3, 12, 15),

> > +	/* DDR4 Only */

> > +	ARRIA_DDR_CONFIG(1, 4, 10, 14),

> > +	ARRIA_DDR_CONFIG(1, 4, 10, 15),

> > +	ARRIA_DDR_CONFIG(1, 4, 10, 16),

> > +	ARRIA_DDR_CONFIG(1, 4, 10, 17),

> > +};

> > +

> > +static int match_ddr_conf(u32 ddr_conf)

> > +{

> > +	int i;

> > +/

> > +	for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {

> > +		if (ddr_conf == ddr_config[i])

> > +			return i;

> > +	}

> > +	return 0;

> > +}

> > +

> > +/* Check whether SDRAM is successfully Calibrated */

> > +static int is_sdram_cal_success(void)

> > +{

> > +	return readl(&socfpga_ecc_hmc_base->ddrcalstat);

> > +}

> > +

> > +static unsigned char ddr_get_bit(u32 ereg, unsigned char bit)

> > +{

> > +	u32 reg = readl(ereg);

> > +

> > +	return (reg & BIT(bit)) ? 1 : 0;

> > +}

> > +

> > +static unsigned char ddr_wait_bit(u32 ereg, u32 bit,

> > +			   u32 expected, u32 timeout_usec)

> > +{

> > +	u32 tmr;

> > +

> > +	for (tmr = 0; tmr < timeout_usec; tmr += 100) {

> > +		udelay(100);

> > +		WATCHDOG_RESET();

> > +		if (ddr_get_bit(ereg, bit) == expected)

> > +			return 0;

> > +	}

> > +

> > +	return 1;

> > +}

> > +

> > +static void ddr_delay(u32 delay)

> > +{

> > +	int tmr;

> > +

> > +	for (tmr = 0; tmr < delay; tmr++) {

> > +		mdelay(1);

> > +		WATCHDOG_RESET();

> > +	}

> > +}

> > +

> > +static int emif_clear(void)

> > +{

> > +	u32 i = DDR_MAX_TRIES;

> > +	u8 ret = 0;

> > +

> > +	writel(0, DDR_REG_CORE2SEQ);

> > +

> > +	do {

> > +		ret = !wait_for_bit(__func__, (u32

> > *)DDR_REG_SEQ2CORE,

> > +				   SEQ2CORE_MASK, 1, 50, 0);

> > +	} while (ret && (--i > 0));

> > +

> > +	return !i;

> > +}

> > +

> > +static int emif_reset(void)

> > +{

> > +	u32 c2s, s2c;

> > +

> > +	c2s = readl(DDR_REG_CORE2SEQ);

> > +	s2c = readl(DDR_REG_SEQ2CORE);

> > +

> > +	debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x

> > dst=%08x\n",

> > +	     c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),

> > +	     readl(IO48_MMR_NIOS2_RESERVE1),

> > +	     readl(IO48_MMR_NIOS2_RESERVE2),

> > +	     readl(IO48_MMR_DRAMSTS));

> > +

> > +	if ((s2c & SEQ2CORE_MASK) && emif_clear()) {

> > +		printf("failed emif_clear()\n");

> > +		return -EPERM;

> > +	}

> > +

> > +	writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);

> > +

> > +	if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT,

> > 0, 1000000)) {

> > +		printf("emif_reset failed to see interrupt

> > acknowledge\n");

> > +		return -EPERM;

> > +	} else {

> > +		printf("emif_reset interrupt acknowledged\n");

> > +	}

> > +

> > +	if (emif_clear()) {

> > +		printf("emif_clear() failed\n");

> Use debug() instead of all the printf()'s.

> 

Okay.
> > 

> > +		return -EPERM;

> > +	}

> > +	debug("emif_reset interrupt cleared\n");

> > +

> > +	debug("nr0=%08x nr1=%08x nr2=%08x\n",

> > +	     readl(IO48_MMR_NIOS2_RESERVE0),

> > +	     readl(IO48_MMR_NIOS2_RESERVE1),

> > +	     readl(IO48_MMR_NIOS2_RESERVE2));

> > +

> > +	return 0;

> emif_reset() has all these return values, but the actual call to

> emif_reset() is not checking the values at all.

> 

Okay, i will add checking to emif_reset().
> > 

> > +}

> > +

> > +static int ddr_setup(void)

> > +{

> > +	int i, j, ddr_setup_complete = 0;

> > +

> > +	/* Try 3 times to do a calibration */

> > +	for (i = 0; (i < 3) && !ddr_setup_complete; i++) {

> > +		WATCHDOG_RESET();

> > +

> > +		/* A delay to wait for calibration bit to set */

> > +		for (j = 0; (j < 10) && !ddr_setup_complete; j++)

> > {

> > +			ddr_delay(500);

> Looks like all ddr_delay() is doing is call to 1ms delay, and the max

> delay is 5s. Looks like you can rid of the ddr_delay() function and

> do

> the wait here.

> 

Okay.
> > 

> > +			ddr_setup_complete =

> > is_sdram_cal_success();

> > +		}

> > +

> > +		if (!ddr_setup_complete)

> > +			emif_reset();

> > +	}

> > +

> > +	if (!ddr_setup_complete) {

> > +		puts("Error: Could Not Calibrate SDRAM\n");

> > +		return -EPERM;

> > +	}

> Move this block of code up to where you did the check for

> !ddr_setup_complete the first time.

> 

This block of codes is located here has its purpose, which return
calibration failed after 3 times trying calibration and emif reset(also
depend on the status checking with !ddr_setup_complete).
> > 

> > +

> > +	return 0;

> > +}

> > +

> > +/* Function to startup the SDRAM*/

> > +static int sdram_startup(void)

> > +{

> > +	/* Release NOC ddr scheduler from reset */

> > +	socfpga_reset_deassert_noc_ddr_scheduler();

> > +

> > +	/* Bringup the DDR (calibration and configuration) */

> > +	return ddr_setup();

> > +}

> > +

> > +static unsigned long long sdram_size_calc(void)

> Use uint64_t

> 

Okay.
> > 

> > +{

> > +	u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);

> > +

> > +	unsigned long long size = BIT(((dramaddrw &

> uint64_t

> 

Okay.
> > 

> > +		IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK) >>

> > +		IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT) +

> > +		((dramaddrw &

> > +		IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK)

> > >>

> > +		IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT

> > ) +

> > +		((dramaddrw &

> > +		IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>

> > +		IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +

> > +		((dramaddrw &

> > +		IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>

> > +		IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT) +

> > +		(dramaddrw &

> > IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK));

> > +

> > +	size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &

> > +		       ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));

> Should add a debug statement here for the size.

> 

Okay.
> > 

> > +

> > +	return size;

> > +}

> > +

> > +/* Function to initialize SDRAM MMR and NOC DDR scheduler*/

> > +static void sdram_mmr_init(void)

> > +{

> > +	u32 update_value, io48_value;

> > +	u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0);

> > +	u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1);

> > +	u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);

> > +	u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0);

> > +	u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1);

> > +	u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2);

> > +	u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3);

> > +	u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4);

> > +	u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9);

> > +	u32 ddrioctl;

> > +

> > +	/*

> > +	 * Configure the DDR IO size [0xFFCFB008]

> > +	 * niosreserve0: Used to indicate DDR width &

> > +	 *	bit[7:0] = Number of data bits (0x20 for 32bit)

> > +	 *	bit[8]   = 1 if user-mode OCT is present

> > +	 *	bit[9]   = 1 if warm reset compiled into EMIF

> > Cal Code

> > +	 *	bit[10]  = 1 if warm reset is on during

> > generation in EMIF Cal

> > +	 * niosreserve1: IP ADCDS version encoded as 16 bit value

> > +	 *	bit[2:0] = Variant (0=not special,1=FAE beta,

> > 2=Customer beta,

> > +	 *			    3=EAP, 4-6 are reserved)

> > +	 *	bit[5:3] = Service Pack # (e.g. 1)

> > +	 *	bit[9:6] = Minor Release #

> > +	 *	bit[14:10] = Major Release #

> > +	 */

> > +	if ((socfpga_io48_mmr_base->niosreserve1 >> 6) & 0x1FF) {

> > +		update_value = readl(&socfpga_io48_mmr_base-

> > >niosreserve0);

> > +		writel(((update_value & 0xFF) >> 5),

> > +		       &socfpga_ecc_hmc_base->ddrioctrl);

> > +	}

> > +

> > +	ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);

> > +

> > +	/* Set the DDR Configuration [0xFFD12400] */

> > +	io48_value = ARRIA_DDR_CONFIG(

> > +			((ctrlcfg1 &

> > +			IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK) >>

> > +			IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT),

> > +			((dramaddrw &

> > +			IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MAS

> > K) >>

> > +			IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHI

> > FT) +

> > +			((dramaddrw &

> > +			IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WID

> > TH_MASK) >>

> > +			IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WID

> > TH_SHIFT),

> > +			(dramaddrw &

> > +			IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK

> > ),

> > +			((dramaddrw &

> > +			IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK

> > ) >>

> > +			IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIF

> > T));

> > +

> > +	update_value = match_ddr_conf(io48_value);

> > +	if (update_value)

> > +		writel(update_value,

> > +		&socfpga_noc_ddr_scheduler_base-

> > >ddr_t_main_scheduler_ddrconf);

> > +

> > +	/*

> > +	 * Configure DDR timing [0xFFD1240C]

> > +	 *  RDTOMISS = tRTP + tRP + tRCD - BL/2

> > +	 *  WRTOMISS = WL + tWR + tRP + tRCD and

> > +	 *    WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns  so...

> > +	 *  First part of equation is in memory clock units so

> > divide by 2

> > +	 *  for HMC clock units. 1066MHz is close to 1ns so use 15

> > directly.

> > +	 *  WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr +

> > tRP + tRCD

> > +	 */

> > +	u32 ctrlcfg0_cfg_ctrl_burst_len =

> > +		(ctrlcfg0 &

> > IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK) >>

> > +		IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT;

> > +

> > +	u32 caltim0_cfg_act_to_rdwr = caltim0 &

> > +		IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK;

> > +

> > +	u32 caltim0_cfg_act_to_act =

> > +		(caltim0 &

> > IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK) >>

> > +		IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT;

> > +

> > +	u32 caltim0_cfg_act_to_act_db =

> > +		(caltim0 &

> > +		IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK)

> > >>

> > +		IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT

> > ;

> > +

> > +	u32 caltim1_cfg_rd_to_wr =

> > +		(caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK)

> > >>

> > +		IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT;

> > +

> > +	u32 caltim1_cfg_rd_to_rd_dc =

> > +		(caltim1 &

> > IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK) >>

> > +		IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT;

> > +

> > +	u32 caltim1_cfg_rd_to_wr_dc =

> > +		(caltim1 &

> > IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK) >>

> > +		IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT;

> > +

> > +	u32 caltim2_cfg_rd_to_pch =

> > +		(caltim2 & IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK)

> > >>

> > +		IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT;

> > +

> > +	u32 caltim3_cfg_wr_to_rd =

> > +		(caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK)

> > >>

> > +		IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT;

> > +

> > +	u32 caltim3_cfg_wr_to_rd_dc =

> > +		(caltim3 &

> > IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK) >>

> > +		IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT;

> > +

> > +	u32 caltim4_cfg_pch_to_valid =

> > +		(caltim4 &

> > IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK) >>

> > +		IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT;

> > +

> > +	u32 caltim9_cfg_4_act_to_act = caltim9 &

> > +		IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK;

> > +

> > +	update_value = (caltim2_cfg_rd_to_pch

> > +  caltim4_cfg_pch_to_valid +

> > +			caltim0_cfg_act_to_rdwr -

> > +			(ctrlcfg0_cfg_ctrl_burst_len >> 2));

> > +

> > +	io48_value = ((((socfpga_io48_mmr_base->dramtiming0 &

> > +		      ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2

> > + 15 +

> > +		      (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -

> > +		      /* Up to here was in memory cycles so divide

> > by 2 */

> > +		      caltim1_cfg_rd_to_wr +

> > caltim0_cfg_act_to_rdwr +

> > +		      caltim4_cfg_pch_to_valid);

> > +

> > +	writel(((caltim0_cfg_act_to_act <<

> > +			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT

> > _LSB) |

> > +		(update_value <<

> > +			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS

> > _LSB) |

> > +		(io48_value <<

> > +			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS

> > _LSB) |

> > +		((ctrlcfg0_cfg_ctrl_burst_len >> 2) <<

> > +			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN

> > _LSB) |

> > +		(caltim1_cfg_rd_to_wr <<

> > +			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_L

> > SB) |

> > +		(caltim3_cfg_wr_to_rd <<

> > +			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_L

> > SB) |

> > +		(((ddrioctl == 1) ? 1 : 0) <<

> > +			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_

> > LSB)),

> > +		&socfpga_noc_ddr_scheduler_base->

> > +			ddr_t_main_scheduler_ddrtiming);

> > +

> > +	/* Configure DDR mode [0xFFD12410] [precharge = 0] */

> > +	writel(((ddrioctl ? 0 : 1) <<

> > +		ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB

> > ),

> > +		&socfpga_noc_ddr_scheduler_base-

> > >ddr_t_main_scheduler_ddrmode);

> > +

> > +	/* Configure the read latency [0xFFD12414] */

> > +	writel(((socfpga_io48_mmr_base->dramtiming0 &

> > +		ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +

> > +		DDR_READ_LATENCY_DELAY,

> > +		&socfpga_noc_ddr_scheduler_base->

> > +			ddr_t_main_scheduler_readlatency);

> > +

> > +	/*

> > +	 * Configuring timing values concerning activate commands

> > +	 * [0xFFD12438] [FAWBANK alway 1 because always 4 bank

> > DDR]

> > +	 */

> > +	writel(((caltim0_cfg_act_to_act_db <<

> > +			ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB)

> > |

> > +		(caltim9_cfg_4_act_to_act <<

> > +			ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB)

> > |

> > +		(ARRIA10_SDR_ACTIVATE_FAWBANK <<

> > +			ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_L

> > SB)),

> > +		&socfpga_noc_ddr_scheduler_base-

> > >ddr_t_main_scheduler_activate);

> > +

> > +	/*

> > +	 * Configuring timing values concerning device to device

> > data bus

> > +	 * ownership change [0xFFD1243C]

> > +	 */

> > +	writel(((caltim1_cfg_rd_to_rd_dc <<

> > +			ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD

> > _LSB) |

> > +		(caltim1_cfg_rd_to_wr_dc <<

> > +			ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR

> > _LSB) |

> > +		(caltim3_cfg_wr_to_rd_dc <<

> > +			ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD

> > _LSB)),

> > +		&socfpga_noc_ddr_scheduler_base-

> > >ddr_t_main_scheduler_devtodev);

> > +

> > +	/* Enable or disable the SDRAM ECC */

> > +	if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) {

> > +		setbits_le32(&socfpga_ecc_hmc_base->eccctrl,

> > +			     (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_S

> > ET_MSK |

> > +			      ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_M

> > SK |

> > +			      ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MS

> > K));

> > +		clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,

> > +			     (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_S

> > ET_MSK |

> > +			      ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_M

> > SK));

> > +		setbits_le32(&socfpga_ecc_hmc_base->eccctrl2,

> > +			     (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_M

> > SK |

> > +			      ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_M

> > SK));

> > +	} else {

> > +		clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,

> > +			     (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_S

> > ET_MSK |

> > +			      ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_M

> > SK |

> > +			      ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MS

> > K));

> > +		clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,

> > +			     (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_M

> > SK |

> > +			      ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_M

> > SK));

> > +	}

> > +}

> > +

> > +struct firewall_entry {

> > +	const char *prop_name;

> > +	const u32 cfg_addr;

> > +	const u32 en_addr;

> > +	const u32 en_bit;

> > +};

> > +#define FW_MPU_FPGA_ADDRESS \

> > +	((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\

> > +	SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)

> > +

> > +#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(ADDR) \

> > +		(SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + \

> > +		offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,

> > ADDR))

> > +

> > +#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(ADDR) \

> > +		(SOCFPGA_SDR_FIREWALL_L3_ADDRESS + \

> > +		offsetof(struct socfpga_noc_fw_ddr_l3, ADDR))

> > +

> > +const struct firewall_entry firewall_table[] = {

> > +	{

> > +		"altr,mpu0",

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpure

> > gion0addr),

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enabl

> > e),

> > +		ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK

> > +	},

> > +	{

> > +		"altr,mpu1",

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpure

> > gion1addr),

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enabl

> > e),

> > +		ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK

> > +	},

> > +	{

> > +		"altr,mpu2",

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpure

> > gion2addr),

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enabl

> > e),

> > +		ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK

> > +	},

> > +	{

> > +		"altr,mpu3",

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpure

> > gion3addr),

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enabl

> > e),

> > +		ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK

> > +	},

> > +	{

> > +		"altr,l3-0",

> > +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion0a

> > ddr),

> > +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),

> > +		ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK

> > +	},

> > +	{

> > +		"altr,l3-1",

> > +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion1a

> > ddr),

> > +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),

> > +		ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK

> > +	},

> > +	{

> > +		"altr,l3-2",

> > +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion2a

> > ddr),

> > +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),

> > +		ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK

> > +	},

> > +	{

> > +		"altr,l3-3",

> > +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion3a

> > ddr),

> > +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),

> > +		ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK

> > +	},

> > +	{

> > +		"altr,l3-4",

> > +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion4a

> > ddr),

> > +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),

> > +		ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK

> > +	},

> > +	{

> > +		"altr,l3-5",

> > +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion5a

> > ddr),

> > +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),

> > +		ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK

> > +	},

> > +	{

> > +		"altr,l3-6",

> > +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion6a

> > ddr),

> > +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),

> > +		ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK

> > +	},

> > +	{

> > +		"altr,l3-7",

> > +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion7a

> > ddr),

> > +		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),

> > +		ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK

> > +	},

> > +	{

> > +		"altr,fpga2sdram0-0",

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET

> > +		(fpga2sdram0region0addr),

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enabl

> > e),

> > +		ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK

> > +	},

> > +	{

> > +		"altr,fpga2sdram0-1",

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET

> > +		(fpga2sdram0region1addr),

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enabl

> > e),

> > +		ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK

> > +	},

> > +	{

> > +		"altr,fpga2sdram0-2",

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET

> > +		(fpga2sdram0region2addr),

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enabl

> > e),

> > +		ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK

> > +	},

> > +	{

> > +		"altr,fpga2sdram0-3",

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET

> > +		(fpga2sdram0region3addr),

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enabl

> > e),

> > +		ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK

> > +	},

> > +	{

> > +		"altr,fpga2sdram1-0",

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET

> > +		(fpga2sdram1region0addr),

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enabl

> > e),

> > +		ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK

> > +	},

> > +	{

> > +		"altr,fpga2sdram1-1",

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET

> > +		(fpga2sdram1region1addr),

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enabl

> > e),

> > +		ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK

> > +	},

> > +	{

> > +		"altr,fpga2sdram1-2",

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET

> > +		(fpga2sdram1region2addr),

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enabl

> > e),

> > +		ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK

> > +	},

> > +	{

> > +		"altr,fpga2sdram1-3",

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET

> > +		(fpga2sdram1region3addr),

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enabl

> > e),

> > +		ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK

> > +	},

> > +	{

> > +		"altr,fpga2sdram2-0",

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET

> > +		(fpga2sdram2region0addr),

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enabl

> > e),

> > +		ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK

> > +	},

> > +	{

> > +		"altr,fpga2sdram2-1",

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET

> > +		(fpga2sdram2region1addr),

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enabl

> > e),

> > +		ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK

> > +	},

> > +	{

> > +		"altr,fpga2sdram2-2",

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET

> > +		(fpga2sdram2region2addr),

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enabl

> > e),

> > +		ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK

> > +	},

> > +	{

> > +		"altr,fpga2sdram2-3",

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET

> > +		(fpga2sdram2region3addr),

> > +		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enabl

> > e),

> > +		ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK

> > +	},

> > +

> > +};

> > +

> > +static int of_sdram_firewall_setup(const void *blob)

> > +{

> > +	int child, i, node;

> > +	u32 start_end[2];

> > +

> > +	node = fdtdec_next_compatible(blob, 0,

> > COMPAT_ALTERA_SOCFPGA_NOC);

> > +	if (node < 0)

> > +		return -ENXIO;

> > +

> > +	child = fdt_first_subnode(blob, node);

> > +	if (child < 0)

> > +		return -ENXIO;

> > +

> > +	/* set to default state */

> > +	writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base-

> > >enable);

> > +	writel(0, &socfpga_noc_fw_ddr_l3_base->enable);

> > +

> > +

> > +	for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {

> > +		if (!fdtdec_get_int_array(blob, child,

> > +					  firewall_table[i].prop_n

> > ame,

> > +					  start_end, 2)) {

> > +			writel((start_end[0] &

> > ALT_NOC_FW_DDR_ADDR_MASK) |

> > +				(start_end[1] <<

> > ALT_NOC_FW_DDR_END_ADDR_LSB),

> > +				 firewall_table[i].cfg_addr);

> > +			setbits_le32(firewall_table[i].en_addr,

> > +				     firewall_table[i].en_bit);

> > +		}

> > +	}

> > +

> > +	return 0;

> > +}

> > +

> > +int ddr_calibration_sequence(void)

> > +{

> > +	WATCHDOG_RESET();

> > +

> > +	/* Check to see if SDRAM cal was success */

> > +	if (sdram_startup()) {

> > +		puts("DDRCAL: Failed\n");

> > +		return -EPERM;

> > +	}

> > +

> > +	puts("DDRCAL: Success\n");

> > +

> > +	WATCHDOG_RESET();

> > +

> > +	/* initialize the MMR register */

> > +	sdram_mmr_init();

> > +

> > +	/* assigning the SDRAM size */

> > +	unsigned long long size = sdram_size_calc();

> > +

> > +	/* If a weird value, use default Config size */

> > +	/* Up to 2GB is supported, 2GB would be used if more than

> > that */

> Fix comment style.

> 

Okay.
> > 

> > +	if (size <= 0)

> Can size ever be less than zero?

> 

This is invalid/weird value returned from calculation.

> Dinh

Patch

diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
index 137e073..33f830b 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -10,6 +10,8 @@ 
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include <asm/arch/sdram_gen5.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/sdram_arria10.h>
 #endif
 
 #endif
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
index 1d7b7c1..e7a2503 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
@@ -8,6 +8,7 @@ 
 #define _SOCFPGA_SDRAM_ARRIA10_H_
 
 #ifndef __ASSEMBLY__
+int ddr_calibration_sequence(void);
 
 struct socfpga_ecc_hmc {
 	u32 ip_rev_id;
@@ -204,6 +205,7 @@  struct socfpga_io48_mmr {
 	u32 niosreserve1;
 	u32 niosreserve2;
 };
+
 #endif /*__ASSEMBLY__*/
 
 #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK		0x1F000000
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index ac4ab85..02f8b7c 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -10,4 +10,5 @@ 
 
 ifdef CONFIG_ALTERA_SDRAM
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
 endif
diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c
new file mode 100644
index 0000000..be8aff3
--- /dev/null
+++ b/drivers/ddr/altera/sdram_arria10.c
@@ -0,0 +1,736 @@ 
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <wait_bit.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/sdram.h>
+#include <linux/kernel.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_mmr_init(void);
+static unsigned long long sdram_size_calc(void);
+
+/* FAWBANK - Number of Bank of a given device involved in the FAW period. */
+#define ARRIA10_SDR_ACTIVATE_FAWBANK	(0x1)
+
+#define ARRIA_DDR_CONFIG(A, B, C, R) \
+	(((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
+#define DDR_CONFIG_ELEMENTS	ARRAY_SIZE(ddr_config)
+#define DDR_REG_SEQ2CORE        0xFFD0507C
+#define DDR_REG_CORE2SEQ        0xFFD05078
+#define DDR_READ_LATENCY_DELAY	40
+#define DDR_SIZE_2GB_HEX	0x80000000
+#define DDR_MAX_TRIES		0x00100000
+
+#define IO48_MMR_DRAMSTS	0xFFCFA0EC
+#define IO48_MMR_NIOS2_RESERVE0	0xFFCFA110
+#define IO48_MMR_NIOS2_RESERVE1	0xFFCFA114
+#define IO48_MMR_NIOS2_RESERVE2	0xFFCFA118
+
+#define SEQ2CORE_MASK		0xF
+#define CORE2SEQ_INT_REQ	0xF
+#define SEQ2CORE_INT_RESP_BIT	3
+
+static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
+		(void *)SOCFPGA_SDR_ADDRESS;
+static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
+		(void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
+static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
+		*socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
+		(void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
+static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
+		(void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
+static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
+		(void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
+
+/* The followring are the supported configurations */
+static u32 ddr_config[] = {
+	/* Chip - Row - Bank - Column Style */
+	/* All Types */
+	ARRIA_DDR_CONFIG(0, 3, 10, 12),
+	ARRIA_DDR_CONFIG(0, 3, 10, 13),
+	ARRIA_DDR_CONFIG(0, 3, 10, 14),
+	ARRIA_DDR_CONFIG(0, 3, 10, 15),
+	ARRIA_DDR_CONFIG(0, 3, 10, 16),
+	ARRIA_DDR_CONFIG(0, 3, 10, 17),
+	/* LPDDR x16 */
+	ARRIA_DDR_CONFIG(0, 3, 11, 14),
+	ARRIA_DDR_CONFIG(0, 3, 11, 15),
+	ARRIA_DDR_CONFIG(0, 3, 11, 16),
+	ARRIA_DDR_CONFIG(0, 3, 12, 15),
+	/* DDR4 Only */
+	ARRIA_DDR_CONFIG(0, 4, 10, 14),
+	ARRIA_DDR_CONFIG(0, 4, 10, 15),
+	ARRIA_DDR_CONFIG(0, 4, 10, 16),
+	ARRIA_DDR_CONFIG(0, 4, 10, 17),	/* 14 */
+	/* Chip - Bank - Row - Column Style */
+	ARRIA_DDR_CONFIG(1, 3, 10, 12),
+	ARRIA_DDR_CONFIG(1, 3, 10, 13),
+	ARRIA_DDR_CONFIG(1, 3, 10, 14),
+	ARRIA_DDR_CONFIG(1, 3, 10, 15),
+	ARRIA_DDR_CONFIG(1, 3, 10, 16),
+	ARRIA_DDR_CONFIG(1, 3, 10, 17),
+	ARRIA_DDR_CONFIG(1, 3, 11, 14),
+	ARRIA_DDR_CONFIG(1, 3, 11, 15),
+	ARRIA_DDR_CONFIG(1, 3, 11, 16),
+	ARRIA_DDR_CONFIG(1, 3, 12, 15),
+	/* DDR4 Only */
+	ARRIA_DDR_CONFIG(1, 4, 10, 14),
+	ARRIA_DDR_CONFIG(1, 4, 10, 15),
+	ARRIA_DDR_CONFIG(1, 4, 10, 16),
+	ARRIA_DDR_CONFIG(1, 4, 10, 17),
+};
+
+static int match_ddr_conf(u32 ddr_conf)
+{
+	int i;
+
+	for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
+		if (ddr_conf == ddr_config[i])
+			return i;
+	}
+	return 0;
+}
+
+/* Check whether SDRAM is successfully Calibrated */
+static int is_sdram_cal_success(void)
+{
+	return readl(&socfpga_ecc_hmc_base->ddrcalstat);
+}
+
+static unsigned char ddr_get_bit(u32 ereg, unsigned char bit)
+{
+	u32 reg = readl(ereg);
+
+	return (reg & BIT(bit)) ? 1 : 0;
+}
+
+static unsigned char ddr_wait_bit(u32 ereg, u32 bit,
+			   u32 expected, u32 timeout_usec)
+{
+	u32 tmr;
+
+	for (tmr = 0; tmr < timeout_usec; tmr += 100) {
+		udelay(100);
+		WATCHDOG_RESET();
+		if (ddr_get_bit(ereg, bit) == expected)
+			return 0;
+	}
+
+	return 1;
+}
+
+static void ddr_delay(u32 delay)
+{
+	int tmr;
+
+	for (tmr = 0; tmr < delay; tmr++) {
+		mdelay(1);
+		WATCHDOG_RESET();
+	}
+}
+
+static int emif_clear(void)
+{
+	u32 i = DDR_MAX_TRIES;
+	u8 ret = 0;
+
+	writel(0, DDR_REG_CORE2SEQ);
+
+	do {
+		ret = !wait_for_bit(__func__, (u32 *)DDR_REG_SEQ2CORE,
+				   SEQ2CORE_MASK, 1, 50, 0);
+	} while (ret && (--i > 0));
+
+	return !i;
+}
+
+static int emif_reset(void)
+{
+	u32 c2s, s2c;
+
+	c2s = readl(DDR_REG_CORE2SEQ);
+	s2c = readl(DDR_REG_SEQ2CORE);
+
+	debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
+	     c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
+	     readl(IO48_MMR_NIOS2_RESERVE1),
+	     readl(IO48_MMR_NIOS2_RESERVE2),
+	     readl(IO48_MMR_DRAMSTS));
+
+	if ((s2c & SEQ2CORE_MASK) && emif_clear()) {
+		printf("failed emif_clear()\n");
+		return -EPERM;
+	}
+
+	writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
+
+	if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) {
+		printf("emif_reset failed to see interrupt acknowledge\n");
+		return -EPERM;
+	} else {
+		printf("emif_reset interrupt acknowledged\n");
+	}
+
+	if (emif_clear()) {
+		printf("emif_clear() failed\n");
+		return -EPERM;
+	}
+	debug("emif_reset interrupt cleared\n");
+
+	debug("nr0=%08x nr1=%08x nr2=%08x\n",
+	     readl(IO48_MMR_NIOS2_RESERVE0),
+	     readl(IO48_MMR_NIOS2_RESERVE1),
+	     readl(IO48_MMR_NIOS2_RESERVE2));
+
+	return 0;
+}
+
+static int ddr_setup(void)
+{
+	int i, j, ddr_setup_complete = 0;
+
+	/* Try 3 times to do a calibration */
+	for (i = 0; (i < 3) && !ddr_setup_complete; i++) {
+		WATCHDOG_RESET();
+
+		/* A delay to wait for calibration bit to set */
+		for (j = 0; (j < 10) && !ddr_setup_complete; j++) {
+			ddr_delay(500);
+			ddr_setup_complete = is_sdram_cal_success();
+		}
+
+		if (!ddr_setup_complete)
+			emif_reset();
+	}
+
+	if (!ddr_setup_complete) {
+		puts("Error: Could Not Calibrate SDRAM\n");
+		return -EPERM;
+	}
+
+	return 0;
+}
+
+/* Function to startup the SDRAM*/
+static int sdram_startup(void)
+{
+	/* Release NOC ddr scheduler from reset */
+	socfpga_reset_deassert_noc_ddr_scheduler();
+
+	/* Bringup the DDR (calibration and configuration) */
+	return ddr_setup();
+}
+
+static unsigned long long sdram_size_calc(void)
+{
+	u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
+
+	unsigned long long size = BIT(((dramaddrw &
+		IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK) >>
+		IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT) +
+		((dramaddrw &
+		IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
+		IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT) +
+		((dramaddrw &
+		IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
+		IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
+		((dramaddrw &
+		IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
+		IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT) +
+		(dramaddrw & IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK));
+
+	size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
+		       ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));
+
+	return size;
+}
+
+/* Function to initialize SDRAM MMR and NOC DDR scheduler*/
+static void sdram_mmr_init(void)
+{
+	u32 update_value, io48_value;
+	u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0);
+	u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1);
+	u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
+	u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0);
+	u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1);
+	u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2);
+	u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3);
+	u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4);
+	u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9);
+	u32 ddrioctl;
+
+	/*
+	 * Configure the DDR IO size [0xFFCFB008]
+	 * niosreserve0: Used to indicate DDR width &
+	 *	bit[7:0] = Number of data bits (0x20 for 32bit)
+	 *	bit[8]   = 1 if user-mode OCT is present
+	 *	bit[9]   = 1 if warm reset compiled into EMIF Cal Code
+	 *	bit[10]  = 1 if warm reset is on during generation in EMIF Cal
+	 * niosreserve1: IP ADCDS version encoded as 16 bit value
+	 *	bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
+	 *			    3=EAP, 4-6 are reserved)
+	 *	bit[5:3] = Service Pack # (e.g. 1)
+	 *	bit[9:6] = Minor Release #
+	 *	bit[14:10] = Major Release #
+	 */
+	if ((socfpga_io48_mmr_base->niosreserve1 >> 6) & 0x1FF) {
+		update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
+		writel(((update_value & 0xFF) >> 5),
+		       &socfpga_ecc_hmc_base->ddrioctrl);
+	}
+
+	ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);
+
+	/* Set the DDR Configuration [0xFFD12400] */
+	io48_value = ARRIA_DDR_CONFIG(
+			((ctrlcfg1 &
+			IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK) >>
+			IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT),
+			((dramaddrw &
+			IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
+			IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
+			((dramaddrw &
+			IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
+			IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT),
+			(dramaddrw &
+			IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK),
+			((dramaddrw &
+			IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
+			IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT));
+
+	update_value = match_ddr_conf(io48_value);
+	if (update_value)
+		writel(update_value,
+		&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf);
+
+	/*
+	 * Configure DDR timing [0xFFD1240C]
+	 *  RDTOMISS = tRTP + tRP + tRCD - BL/2
+	 *  WRTOMISS = WL + tWR + tRP + tRCD and
+	 *    WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns  so...
+	 *  First part of equation is in memory clock units so divide by 2
+	 *  for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
+	 *  WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
+	 */
+	u32 ctrlcfg0_cfg_ctrl_burst_len =
+		(ctrlcfg0 & IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK) >>
+		IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT;
+
+	u32 caltim0_cfg_act_to_rdwr = caltim0 &
+		IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK;
+
+	u32 caltim0_cfg_act_to_act =
+		(caltim0 & IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK) >>
+		IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT;
+
+	u32 caltim0_cfg_act_to_act_db =
+		(caltim0 &
+		IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK) >>
+		IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT;
+
+	u32 caltim1_cfg_rd_to_wr =
+		(caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK) >>
+		IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT;
+
+	u32 caltim1_cfg_rd_to_rd_dc =
+		(caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK) >>
+		IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT;
+
+	u32 caltim1_cfg_rd_to_wr_dc =
+		(caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK) >>
+		IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT;
+
+	u32 caltim2_cfg_rd_to_pch =
+		(caltim2 & IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK) >>
+		IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT;
+
+	u32 caltim3_cfg_wr_to_rd =
+		(caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK) >>
+		IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT;
+
+	u32 caltim3_cfg_wr_to_rd_dc =
+		(caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK) >>
+		IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT;
+
+	u32 caltim4_cfg_pch_to_valid =
+		(caltim4 & IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK) >>
+		IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT;
+
+	u32 caltim9_cfg_4_act_to_act = caltim9 &
+		IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK;
+
+	update_value = (caltim2_cfg_rd_to_pch +  caltim4_cfg_pch_to_valid +
+			caltim0_cfg_act_to_rdwr -
+			(ctrlcfg0_cfg_ctrl_burst_len >> 2));
+
+	io48_value = ((((socfpga_io48_mmr_base->dramtiming0 &
+		      ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +
+		      (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
+		      /* Up to here was in memory cycles so divide by 2 */
+		      caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr +
+		      caltim4_cfg_pch_to_valid);
+
+	writel(((caltim0_cfg_act_to_act <<
+			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) |
+		(update_value <<
+			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) |
+		(io48_value <<
+			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) |
+		((ctrlcfg0_cfg_ctrl_burst_len >> 2) <<
+			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) |
+		(caltim1_cfg_rd_to_wr <<
+			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) |
+		(caltim3_cfg_wr_to_rd <<
+			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) |
+		(((ddrioctl == 1) ? 1 : 0) <<
+			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)),
+		&socfpga_noc_ddr_scheduler_base->
+			ddr_t_main_scheduler_ddrtiming);
+
+	/* Configure DDR mode [0xFFD12410] [precharge = 0] */
+	writel(((ddrioctl ? 0 : 1) <<
+		ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB),
+		&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);
+
+	/* Configure the read latency [0xFFD12414] */
+	writel(((socfpga_io48_mmr_base->dramtiming0 &
+		ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +
+		DDR_READ_LATENCY_DELAY,
+		&socfpga_noc_ddr_scheduler_base->
+			ddr_t_main_scheduler_readlatency);
+
+	/*
+	 * Configuring timing values concerning activate commands
+	 * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR]
+	 */
+	writel(((caltim0_cfg_act_to_act_db <<
+			ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) |
+		(caltim9_cfg_4_act_to_act <<
+			ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) |
+		(ARRIA10_SDR_ACTIVATE_FAWBANK <<
+			ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)),
+		&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate);
+
+	/*
+	 * Configuring timing values concerning device to device data bus
+	 * ownership change [0xFFD1243C]
+	 */
+	writel(((caltim1_cfg_rd_to_rd_dc <<
+			ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) |
+		(caltim1_cfg_rd_to_wr_dc <<
+			ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) |
+		(caltim3_cfg_wr_to_rd_dc <<
+			ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)),
+		&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev);
+
+	/* Enable or disable the SDRAM ECC */
+	if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) {
+		setbits_le32(&socfpga_ecc_hmc_base->eccctrl,
+			     (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
+			      ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
+			      ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
+		clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
+			     (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
+			      ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK));
+		setbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
+			     (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
+			      ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
+	} else {
+		clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
+			     (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
+			      ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
+			      ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
+		clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
+			     (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
+			      ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
+	}
+}
+
+struct firewall_entry {
+	const char *prop_name;
+	const u32 cfg_addr;
+	const u32 en_addr;
+	const u32 en_bit;
+};
+#define FW_MPU_FPGA_ADDRESS \
+	((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\
+	SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)
+
+#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(ADDR) \
+		(SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + \
+		offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram, ADDR))
+
+#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(ADDR) \
+		(SOCFPGA_SDR_FIREWALL_L3_ADDRESS + \
+		offsetof(struct socfpga_noc_fw_ddr_l3, ADDR))
+
+const struct firewall_entry firewall_table[] = {
+	{
+		"altr,mpu0",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion0addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK
+	},
+	{
+		"altr,mpu1",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion1addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK
+	},
+	{
+		"altr,mpu2",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion2addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK
+	},
+	{
+		"altr,mpu3",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion3addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK
+	},
+	{
+		"altr,l3-0",
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion0addr),
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK
+	},
+	{
+		"altr,l3-1",
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion1addr),
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK
+	},
+	{
+		"altr,l3-2",
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion2addr),
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK
+	},
+	{
+		"altr,l3-3",
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion3addr),
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK
+	},
+	{
+		"altr,l3-4",
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion4addr),
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK
+	},
+	{
+		"altr,l3-5",
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion5addr),
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK
+	},
+	{
+		"altr,l3-6",
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion6addr),
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK
+	},
+	{
+		"altr,l3-7",
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion7addr),
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram0-0",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+		(fpga2sdram0region0addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram0-1",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+		(fpga2sdram0region1addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram0-2",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+		(fpga2sdram0region2addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram0-3",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+		(fpga2sdram0region3addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram1-0",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+		(fpga2sdram1region0addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram1-1",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+		(fpga2sdram1region1addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram1-2",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+		(fpga2sdram1region2addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram1-3",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+		(fpga2sdram1region3addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram2-0",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+		(fpga2sdram2region0addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram2-1",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+		(fpga2sdram2region1addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram2-2",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+		(fpga2sdram2region2addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram2-3",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+		(fpga2sdram2region3addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK
+	},
+
+};
+
+static int of_sdram_firewall_setup(const void *blob)
+{
+	int child, i, node;
+	u32 start_end[2];
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC);
+	if (node < 0)
+		return -ENXIO;
+
+	child = fdt_first_subnode(blob, node);
+	if (child < 0)
+		return -ENXIO;
+
+	/* set to default state */
+	writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);
+	writel(0, &socfpga_noc_fw_ddr_l3_base->enable);
+
+
+	for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {
+		if (!fdtdec_get_int_array(blob, child,
+					  firewall_table[i].prop_name,
+					  start_end, 2)) {
+			writel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) |
+				(start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB),
+				 firewall_table[i].cfg_addr);
+			setbits_le32(firewall_table[i].en_addr,
+				     firewall_table[i].en_bit);
+		}
+	}
+
+	return 0;
+}
+
+int ddr_calibration_sequence(void)
+{
+	WATCHDOG_RESET();
+
+	/* Check to see if SDRAM cal was success */
+	if (sdram_startup()) {
+		puts("DDRCAL: Failed\n");
+		return -EPERM;
+	}
+
+	puts("DDRCAL: Success\n");
+
+	WATCHDOG_RESET();
+
+	/* initialize the MMR register */
+	sdram_mmr_init();
+
+	/* assigning the SDRAM size */
+	unsigned long long size = sdram_size_calc();
+
+	/* If a weird value, use default Config size */
+	/* Up to 2GB is supported, 2GB would be used if more than that */
+	if (size <= 0)
+		gd->ram_size = PHYS_SDRAM_1_SIZE;
+	else if (DDR_SIZE_2GB_HEX <= size)
+		gd->ram_size = DDR_SIZE_2GB_HEX;
+	else
+		gd->ram_size = (u32)size;
+
+	/* setup the dram info within bd */
+	dram_init_banksize();
+
+	if (of_sdram_firewall_setup(gd->fdt_blob))
+		puts("FW: Error Configuring Firewall\n");
+
+	return 0;
+}
+
+void dram_bank_mmu_setup(int bank)
+{
+	bd_t *bd = gd->bd;
+	int	i;
+
+	debug("%s: bank: %d\n", __func__, bank);
+	for (i = bd->bi_dram[bank].start >> 20;
+	     i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
+	     i++) {
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+		set_section_dcache(i, DCACHE_WRITETHROUGH);
+#else
+		set_section_dcache(i, DCACHE_WRITEBACK);
+#endif
+	}
+
+	/* same as above but just that we would want cacheable for ocram too */
+	i = CONFIG_SYS_INIT_RAM_ADDR >> 20;
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+	set_section_dcache(i, DCACHE_WRITETHROUGH);
+#else
+	set_section_dcache(i, DCACHE_WRITEBACK);
+#endif
+}