[U-Boot,v3,15/20] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10

Message ID 1507882137-27841-16-git-send-email-tien.fong.chee@intel.com
State Superseded
Delegated to: Marek Vasut
Headers show
Series
  • Add FPGA, SDRAM, SPL loadfs U-boot & booting to console
Related show

Commit Message

Chee, Tien Fong Oct. 13, 2017, 8:08 a.m.
From: Tien Fong Chee <tien.fong.chee@intel.com>

Enhance preloader header with both additional program length and program
entry offset attributes, which offset is relative to the start of program
header.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/include/mach/boot0.h | 7 +++++++
 1 file changed, 7 insertions(+)

Comments

Dinh Nguyen Oct. 20, 2017, 2:19 p.m. | #1
On 10/13/2017 03:08 AM, tien.fong.chee@intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Enhance preloader header with both additional program length and program
> entry offset attributes, which offset is relative to the start of program
> header.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>  arch/arm/mach-socfpga/include/mach/boot0.h | 7 +++++++
>  1 file changed, 7 insertions(+)
> 

Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>

Dinh

Patch

diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h b/arch/arm/mach-socfpga/include/mach/boot0.h
index e06b548..b21b871 100644
--- a/arch/arm/mach-socfpga/include/mach/boot0.h
+++ b/arch/arm/mach-socfpga/include/mach/boot0.h
@@ -12,6 +12,13 @@ 
 
 	.word	0x1337c0d3;	/* SoCFPGA preloader validation word */
 	.word	0xc01df00d;	/* Header length(2B),flags(1B),version(1B) */
+#ifndef CONFIG_TARGET_SOCFPGA_GEN5
+	.word	0xfeedface;	/* Program length(4B) */
+	.word	0xf00dcafe;	/*
+				 * Program entry offset(4B),relative to
+				 * the start of program header
+				 */
+#endif
 	.word	0xcafec0d3;	/* Simple checksum(2B),spare offset(2B) */
 	nop;