diff mbox series

[U-Boot,v3,02/20] dts: Add FPGA bitstream properties to Arria 10 DTS

Message ID 1507882137-27841-3-git-send-email-tien.fong.chee@intel.com
State Superseded
Delegated to: Marek Vasut
Headers show
Series Add FPGA, SDRAM, SPL loadfs U-boot & booting to console | expand

Commit Message

Chee, Tien Fong Oct. 13, 2017, 8:08 a.m. UTC 
From: Tien Fong Chee <tien.fong.chee@intel.com>

These FPGA bitstream properties would help bootloader to understand
how to configure FPGA and where to look the FPGA RBF files during
booting.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/dts/socfpga_arria10.dtsi | 5 +++++
 1 file changed, 5 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
index 377700d..aeb2be8 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -538,6 +538,11 @@ 
 			clocks = <&l4_mp_clk>;
 			resets = <&rst FPGAMGR_RESET>;
 			reset-names = "fpgamgr";
+			altr,bitstream_periph =
+			 "ghrd_10as066n2.periph.rbf.mkimage";
+			altr,bitstream_core =
+			 "ghrd_10as066n2.core.rbf.mkimage";
+			altr,bitstream_devpart = "0:1";
 		};
 
 		i2c0: i2c@ffc02200 {