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[U-Boot,v3,01/20] ARM: socfpga: Description on FPGA RBF properties at Arria 10 FPGA manager

Message ID 1507882137-27841-2-git-send-email-tien.fong.chee@intel.com
State Superseded
Delegated to: Marek Vasut
Headers show
Series Add FPGA, SDRAM, SPL loadfs U-boot & booting to console | expand

Commit Message

Chee, Tien Fong Oct. 13, 2017, 8:08 a.m. UTC 
From: Tien Fong Chee <tien.fong.chee@intel.com>

This patch adds description on properties about location of FPGA RBFs are
stored, type and functionality of RBF used to configure FPGA.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 11 +++++++++++
 1 file changed, 11 insertions(+)
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Patch

diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
index 2fd8e7a..47c695b 100644
--- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
+++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
@@ -7,6 +7,14 @@  Required properties:
                - The second index is for writing FPGA configuration data.
 - resets     : Phandle and reset specifier for the device's reset.
 - clocks     : Clocks used by the device.
+- altr,bitstream_periph : FPGA peripheral raw binary file which is used to
+                          initialize FPGA IOs, PLL, IO48 and DDR.
+- altr,bitstream_core : FPGA core raw binary file contains FPGA design which is
+			used to program FPGA CRAM and ERAM.
+- altr,bitstream_devpart : Partition of flash device where bitstream files are
+		           stored.
+                           <dev[:part]> - dev is flash device number, part is
+					  flash device partition.
 
 Example:
 
@@ -16,4 +24,7 @@  Example:
 		       0xffcfe400 0x20>;
 		clocks = <&l4_mp_clk>;
 		resets = <&rst FPGAMGR_RESET>;
+		altr,bitstream_periph = "ghrd_10as066n2.periph.rbf.mkimage";
+		altr,bitstream_core = "ghrd_10as066n2.core.rbf.mkimage";
+		altr,bitstream_devpart = "0:1";
 	};