From patchwork Thu Oct 12 20:52:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 825085 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="XkLqSbvk"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yCjk63gg4z9sBW for ; Fri, 13 Oct 2017 07:53:34 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755297AbdJLUwf (ORCPT ); Thu, 12 Oct 2017 16:52:35 -0400 Received: from mail-pf0-f182.google.com ([209.85.192.182]:56214 "EHLO mail-pf0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755201AbdJLUwd (ORCPT ); Thu, 12 Oct 2017 16:52:33 -0400 Received: by mail-pf0-f182.google.com with SMTP id 17so6580023pfn.12 for ; Thu, 12 Oct 2017 13:52:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=omwDLTjhkoV879JbPb4WJXB4tSDpCkA/wkgiWn4TBd0=; b=XkLqSbvk0OrhVNWFcS0g+3K+fS1taCN0OAw9SceIbSEq4dN0fnZJRSf+mvLEaBxKTd BJL1jh6O1B7Ks3CKXfvO4tdiA4XFnJn1sV6Bf4BVe1SHpRC/N/N2+PY+GsqPsv+WHm9s k+Q19ITSsGjSWEUQ8wVcb6ZOLO3bPwdLXpENM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=omwDLTjhkoV879JbPb4WJXB4tSDpCkA/wkgiWn4TBd0=; b=L7/haOmip5xc/SqOlDD8U4FdETT2mUfA/cXhZdZJS2/nzFK9yUNRLe0Gs33x4qUS5k GMjjkGEh5efCow/R/xXr6cRZIsL6cmqCU/Lo5sN4I2zxSQiNy1AG3oMIMFuDVGp+gAnY ZzdFcQTmwFbfsSTFhIMe/9BGfnUDTCgDmNb+JmuoxMxIKV+jYzfSQlz3JUKHLLN0cCzA 3VySvMAoXbk/DrEopaiur+8b15UTTjdwJX59bO6ycZM1vfpkppsrmD2xI/40rty9PKxK iIQuskIUra7wOjKhTjXy1LdvnYJdV601o23YdrhmO2IJZgsVjea+v8lRueARiQRaknhL hJKA== X-Gm-Message-State: AMCzsaXOt111U30Z/Mp6uWDd9wV0d/jYeSIs9LM6YZ66P2ENz1g7ekjF 6BfW7tK9T1QgLbqpSsnDAtCeZw== X-Google-Smtp-Source: AOwi7QDHAqVlGfHfUuqBV45paYfhG2njEy6se9X6NZCLpYZaWtTpUKGlXB6T62+L4YKiqlY2AoUrZA== X-Received: by 10.84.142.101 with SMTP id 92mr1187667plw.254.1507841552582; Thu, 12 Oct 2017 13:52:32 -0700 (PDT) Received: from ban.mtv.corp.google.com ([172.22.113.17]) by smtp.gmail.com with ESMTPSA id h1sm25048704pgp.37.2017.10.12.13.52.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 12 Oct 2017 13:52:32 -0700 (PDT) From: Brian Norris To: Bjorn Helgaas Cc: Rajat Jain , Rob Herring , Mark Rutland , Frank Rowand , Shawn Lin , Heiko Stuebner , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Brian Norris Subject: [PATCH 1/3] Documentation/devicetree: Add pcie-reset-suspend property Date: Thu, 12 Oct 2017 13:52:18 -0700 Message-Id: <20171012205220.130048-2-briannorris@chromium.org> X-Mailer: git-send-email 2.15.0.rc0.271.g36b669edcc-goog In-Reply-To: <20171012205220.130048-1-briannorris@chromium.org> References: <20171012205220.130048-1-briannorris@chromium.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The patch is self-descriptive. I've found that we may need platform-specific behavior for the PERST# signal in system suspend, depending on the type of PCIe endpoints are attached. Signed-off-by: Brian Norris --- Documentation/devicetree/bindings/pci/pci.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt index c77981c5dd18..91339b6d0652 100644 --- a/Documentation/devicetree/bindings/pci/pci.txt +++ b/Documentation/devicetree/bindings/pci/pci.txt @@ -24,3 +24,14 @@ driver implementation may support the following properties: unsupported link speed, for instance, trying to do training for unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2' for gen2, and '1' for gen1. Any other values are invalid. +- pcie-reset-suspend: + If present this property defines whether the PCIe Reset signal (referred to + as PERST#) should be asserted when the system enters low-power suspend modes + (e.g., S3). Depending on the form factor, the associated PCIe + electromechanical specification may specify a particular behavior (e.g., + "PERST# is asserted in advance of the power being switched off in a + power-managed state like S3") or it may be less clear. The net result is + that some endpoints perform better (e.g., lower power consumption) with + PERST# asserted, and others prefer PERST# deasserted. The value must be '0' + or '1', where '0' means do not assert PERST# and '1' means assert PERST#. + When absent, behavior may be platform-specific.