[rs6000] GIMPLE folding for vector compares

Message ID 1507838592.26707.177.camel@brimstone.rchland.ibm.com
State New
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  • [rs6000] GIMPLE folding for vector compares
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Commit Message

Will Schmidt Oct. 12, 2017, 8:03 p.m.
Hi,
    
Add support for gimple folding of vec_cmp_{eq,ge,gt,le,ne} for
the integer data types.
    
This adds a handful of entries to the switch statement in builtin_function_type
for those builtins having unsigned arguments.
    
Three entries are added to vsx.md to enable vcmpne[bhw] instruction, where we
would otherwise generate a vcmpeq + vnor.
    
This patch requires the previously posted "allow integer return type from vector compares" patch.
    
A handful of existing tests required updates to their specified optimization
levels to continue to generate the desired code.  builtins-3-p9.c in particular
has been updated to reflect improved code gen with the higher specified
optimization level.   Testcase coverage is otherwise handled by the already-in-tree
gcc.target/powerpc/fold-vec-cmp-*.c tests.
    
Tested OK on P6 and newer. OK for trunk?
    
Thanks,
-Will
    
[gcc]

2017-10-12  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* config/rs6000/rs6000.c: (rs6000_gimple_fold_builtin) Add support for
	folding of vector compares.  (builtin_function_type) Add compare
	builtins to the list of functions having unsigned arguments.
	* config/rs6000/vsx.md:  Add vcmpne{b,h,w} instructions.

[testsuite]

2017-10-12  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* gcc.target/powerpc/builtins-3-p9.c: Add -O1, update
	expected codegen checks.
	* gcc.target/powerpc/vec-cmp-sel.c: Mark vars as volatile.
	* gcc.target/powerpc/vsu/vec-cmpne-0.c: Add -O1.
	* gcc.target/powerpc/vsu/vec-cmpne-1.c: Add -O1.
	* gcc.target/powerpc/vsu/vec-cmpne-2.c: Add -O1.
	* gcc.target/powerpc/vsu/vec-cmpne-3.c: Add -O1.
	* gcc.target/powerpc/vsu/vec-cmpne-4.c: Add -O1.
	* gcc.target/powerpc/vsu/vec-cmpne-5.c: Add -O1.
	* gcc.target/powerpc/vsu/vec-cmpne-6.c: Add -O1.

Comments

Segher Boessenkool Oct. 13, 2017, 3:05 a.m. | #1
Hi Will,

On Thu, Oct 12, 2017 at 03:03:12PM -0500, Will Schmidt wrote:
> 	* config/rs6000/rs6000.c: (rs6000_gimple_fold_builtin) Add support for
> 	folding of vector compares.  (builtin_function_type) Add compare
> 	builtins to the list of functions having unsigned arguments.
> 	* config/rs6000/vsx.md:  Add vcmpne{b,h,w} instructions.

	* config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Add support for
	folding of vector compares.
	(builtin_function_type): Add compare builtins to the list of functions
	having unsigned arguments.
	* config/rs6000/vsx.md (vcmpneb_spec, vcmpneh_spec, vcmpnew_spec): New.

> +    case ALTIVEC_BUILTIN_VCMPEQUB:
> +    case ALTIVEC_BUILTIN_VCMPEQUH:
> +    case ALTIVEC_BUILTIN_VCMPEQUW:
> +    case P8V_BUILTIN_VCMPEQUD:
> +      {
> +	arg0 = gimple_call_arg (stmt, 0);
> +	arg1 = gimple_call_arg (stmt, 1);
> +	lhs = gimple_call_lhs (stmt);
> +	gimple *g = gimple_build_assign (lhs, EQ_EXPR, arg0, arg1);
> +	gimple_set_location (g, gimple_location (stmt));
> +	gsi_replace (gsi, g, true);
> +	return true;
> +      }

I wonder how much it helps to factor out the bodies here...  So this could
be like:

+    case ALTIVEC_BUILTIN_VCMPEQUB:
+    case ALTIVEC_BUILTIN_VCMPEQUH:
+    case ALTIVEC_BUILTIN_VCMPEQUW:
+    case P8V_BUILTIN_VCMPEQUD:
+      gsi_replace_call_2arg (gsi, EQ_EXPR, stmt);
+      return true;

with

static void
gsi_replace_call_2arg (gimple_stmt_iterator *gsi, tree_code code, gimple *stmt)
{
  tree arg0 = gimple_call_arg (stmt, 0);
  tree arg1 = gimple_call_arg (stmt, 1);
  tree lhs = gimple_call_lhs (stmt);
  gimple *g = gimple_build_assign (lhs, code, arg0, arg1);
  gimple_set_location (g, gimple_location (stmt));
  gsi_replace (gsi, g, true);
}

(But maybe too many other cases need special code?  And it could use a
better name).

>      default:
>  	if (TARGET_DEBUG_BUILTIN)
>  	   fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n",
>  		    fn_code, fn_name1, fn_name2);
>        break;
>      }
> -
>    return false;
>  }

Please drop this part.  Whitespace is good ;-)

> @@ -18112,10 +18188,27 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,

> +      h.uns_p[1]=1;
> +      h.uns_p[2]=1;

+      h.uns_p[1] = 1;
+      h.uns_p[2] = 1;


> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md

> +;; Vector Compare Not Equal Byte (specified/not+eq:)
> +(define_insn "vcmpneb_spec"
> +  [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
> +	 (not:V16QI
> +	   (eq:V16QI (match_operand:V16QI 1 "altivec_register_operand" "v")
> +		     (match_operand:V16QI 2 "altivec_register_operand" "v"))))]
> +  "TARGET_P9_VECTOR"
> +  "vcmpneb %0,%1,%2"
> +  [(set_attr "type" "vecsimple")]
> +)

+  [(set_attr "type" "vecsimple")])

What does "_spec" mean?  That it is not an unspec?  :-)

If a name is not (expected to be) used directly, it should start with *.

Do we still need the unspec version?


Segher
Richard Biener Oct. 13, 2017, 9:36 a.m. | #2
On Thu, Oct 12, 2017 at 10:03 PM, Will Schmidt
<will_schmidt@vnet.ibm.com> wrote:
> Hi,
>
> Add support for gimple folding of vec_cmp_{eq,ge,gt,le,ne} for
> the integer data types.
>
> This adds a handful of entries to the switch statement in builtin_function_type
> for those builtins having unsigned arguments.
>
> Three entries are added to vsx.md to enable vcmpne[bhw] instruction, where we
> would otherwise generate a vcmpeq + vnor.
>
> This patch requires the previously posted "allow integer return type from vector compares" patch.
>
> A handful of existing tests required updates to their specified optimization
> levels to continue to generate the desired code.  builtins-3-p9.c in particular
> has been updated to reflect improved code gen with the higher specified
> optimization level.   Testcase coverage is otherwise handled by the already-in-tree
> gcc.target/powerpc/fold-vec-cmp-*.c tests.
>
> Tested OK on P6 and newer. OK for trunk?
>
> Thanks,
> -Will
>
> [gcc]
>
> 2017-10-12  Will Schmidt  <will_schmidt@vnet.ibm.com>
>
>         * config/rs6000/rs6000.c: (rs6000_gimple_fold_builtin) Add support for
>         folding of vector compares.  (builtin_function_type) Add compare
>         builtins to the list of functions having unsigned arguments.
>         * config/rs6000/vsx.md:  Add vcmpne{b,h,w} instructions.
>
> [testsuite]
>
> 2017-10-12  Will Schmidt  <will_schmidt@vnet.ibm.com>
>
>         * gcc.target/powerpc/builtins-3-p9.c: Add -O1, update
>         expected codegen checks.
>         * gcc.target/powerpc/vec-cmp-sel.c: Mark vars as volatile.
>         * gcc.target/powerpc/vsu/vec-cmpne-0.c: Add -O1.
>         * gcc.target/powerpc/vsu/vec-cmpne-1.c: Add -O1.
>         * gcc.target/powerpc/vsu/vec-cmpne-2.c: Add -O1.
>         * gcc.target/powerpc/vsu/vec-cmpne-3.c: Add -O1.
>         * gcc.target/powerpc/vsu/vec-cmpne-4.c: Add -O1.
>         * gcc.target/powerpc/vsu/vec-cmpne-5.c: Add -O1.
>         * gcc.target/powerpc/vsu/vec-cmpne-6.c: Add -O1.
>
> diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
> index 12ddd97..7e73239 100644
> --- a/gcc/config/rs6000/rs6000.c
> +++ b/gcc/config/rs6000/rs6000.c
> @@ -16605,17 +16605,93 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
>                                            build_int_cst (arg2_type, 0)), arg0);
>          gimple_set_location (g, loc);
>          gsi_replace (gsi, g, true);
>          return true;
>        }
> +    /* Vector compares (integer); EQ, NE, GE, GT, LE.  */
> +    case ALTIVEC_BUILTIN_VCMPEQUB:
> +    case ALTIVEC_BUILTIN_VCMPEQUH:
> +    case ALTIVEC_BUILTIN_VCMPEQUW:
> +    case P8V_BUILTIN_VCMPEQUD:
> +      {
> +       arg0 = gimple_call_arg (stmt, 0);
> +       arg1 = gimple_call_arg (stmt, 1);
> +       lhs = gimple_call_lhs (stmt);
> +       gimple *g = gimple_build_assign (lhs, EQ_EXPR, arg0, arg1);

As said elsewhere this needs to become either

  tree ctype = build_same_sized_truth_vector_type (TREE_TYPE (lhs));
  gimple_build_assign (make_ssa_name (ctype), EQ_EXPR, arg0, arg1)
  gimple_build_assign (lhs, VIEW_CONVERT_EXPR, lhs above);

(eventually the VCE can be elided - try) or

  gimple_build_assign (lhs, VEC_COND_EXPR,
         fold_build2 (EQ_EXPR, ctype, arg0, arg1),
         vector-with-trues, vector-with-falses);

depending on what your target can expand.


> +       gimple_set_location (g, gimple_location (stmt));
> +       gsi_replace (gsi, g, true);
> +       return true;
> +      }
> +    case P9V_BUILTIN_CMPNEB:
> +    case P9V_BUILTIN_CMPNEH:
> +    case P9V_BUILTIN_CMPNEW:
> +      {
> +       arg0 = gimple_call_arg (stmt, 0);
> +       arg1 = gimple_call_arg (stmt, 1);
> +       lhs = gimple_call_lhs (stmt);
> +       gimple *g = gimple_build_assign (lhs, NE_EXPR, arg0, arg1);
> +       gimple_set_location (g, gimple_location (stmt));
> +       gsi_replace (gsi, g, true);
> +       return true;
> +      }
> +    case VSX_BUILTIN_CMPGE_16QI:
> +    case VSX_BUILTIN_CMPGE_U16QI:
> +    case VSX_BUILTIN_CMPGE_8HI:
> +    case VSX_BUILTIN_CMPGE_U8HI:
> +    case VSX_BUILTIN_CMPGE_4SI:
> +    case VSX_BUILTIN_CMPGE_U4SI:
> +    case VSX_BUILTIN_CMPGE_2DI:
> +    case VSX_BUILTIN_CMPGE_U2DI:
> +      {
> +       arg0 = gimple_call_arg (stmt, 0);
> +       arg1 = gimple_call_arg (stmt, 1);
> +       lhs = gimple_call_lhs (stmt);
> +       gimple *g = gimple_build_assign (lhs, GE_EXPR, arg0, arg1);
> +       gimple_set_location (g, gimple_location (stmt));
> +       gsi_replace (gsi, g, true);
> +       return true;
> +      }
> +    case ALTIVEC_BUILTIN_VCMPGTSB:
> +    case ALTIVEC_BUILTIN_VCMPGTUH:
> +    case ALTIVEC_BUILTIN_VCMPGTSH:
> +    case ALTIVEC_BUILTIN_VCMPGTUW:
> +    case ALTIVEC_BUILTIN_VCMPGTSW:
> +    case ALTIVEC_BUILTIN_VCMPGTUB:
> +    case P8V_BUILTIN_VCMPGTUD:
> +    case P8V_BUILTIN_VCMPGTSD:
> +      {
> +       arg0 = gimple_call_arg (stmt, 0);
> +       arg1 = gimple_call_arg (stmt, 1);
> +       lhs = gimple_call_lhs (stmt);
> +       gimple *g = gimple_build_assign (lhs, GT_EXPR, arg0, arg1);
> +       gimple_set_location (g, gimple_location (stmt));
> +       gsi_replace (gsi, g, true);
> +       return true;
> +      }
> +    case VSX_BUILTIN_CMPLE_16QI:
> +    case VSX_BUILTIN_CMPLE_U16QI:
> +    case VSX_BUILTIN_CMPLE_8HI:
> +    case VSX_BUILTIN_CMPLE_U8HI:
> +    case VSX_BUILTIN_CMPLE_4SI:
> +    case VSX_BUILTIN_CMPLE_U4SI:
> +    case VSX_BUILTIN_CMPLE_2DI:
> +    case VSX_BUILTIN_CMPLE_U2DI:
> +      {
> +       arg0 = gimple_call_arg (stmt, 0);
> +       arg1 = gimple_call_arg (stmt, 1);
> +       lhs = gimple_call_lhs (stmt);
> +       gimple *g = gimple_build_assign (lhs, LE_EXPR, arg0, arg1);
> +       gimple_set_location (g, gimple_location (stmt));
> +       gsi_replace (gsi, g, true);
> +       return true;
> +      }
>      default:
>         if (TARGET_DEBUG_BUILTIN)
>            fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n",
>                     fn_code, fn_name1, fn_name2);
>        break;
>      }
> -
>    return false;
>  }
>
>  /* Expand an expression EXP that calls a built-in function,
>     with result going to TARGET if that's convenient
> @@ -18112,10 +18188,27 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
>      case MISC_BUILTIN_UNPACK_TD:
>      case MISC_BUILTIN_UNPACK_V1TI:
>        h.uns_p[0] = 1;
>        break;
>
> +      /* unsigned arguments, bool return (compares).  */
> +    case ALTIVEC_BUILTIN_VCMPEQUB:
> +    case ALTIVEC_BUILTIN_VCMPEQUH:
> +    case ALTIVEC_BUILTIN_VCMPEQUW:
> +    case P8V_BUILTIN_VCMPEQUD:
> +    case VSX_BUILTIN_CMPGE_U16QI:
> +    case VSX_BUILTIN_CMPGE_U8HI:
> +    case VSX_BUILTIN_CMPGE_U4SI:
> +    case VSX_BUILTIN_CMPGE_U2DI:
> +    case ALTIVEC_BUILTIN_VCMPGTUB:
> +    case ALTIVEC_BUILTIN_VCMPGTUH:
> +    case ALTIVEC_BUILTIN_VCMPGTUW:
> +    case P8V_BUILTIN_VCMPGTUD:
> +      h.uns_p[1]=1;
> +      h.uns_p[2]=1;
> +      break;
> +
>        /* unsigned arguments for 128-bit pack instructions.  */
>      case MISC_BUILTIN_PACK_TD:
>      case MISC_BUILTIN_PACK_V1TI:
>        h.uns_p[1] = 1;
>        h.uns_p[2] = 1;
> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
> index 35be5de..baf05ca 100644
> --- a/gcc/config/rs6000/vsx.md
> +++ b/gcc/config/rs6000/vsx.md
> @@ -4449,10 +4449,21 @@
>          UNSPEC_VCMPNEB))]
>    "TARGET_P9_VECTOR"
>    "vcmpneb %0,%1,%2"
>    [(set_attr "type" "vecsimple")])
>
> +;; Vector Compare Not Equal Byte (specified/not+eq:)
> +(define_insn "vcmpneb_spec"
> +  [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
> +        (not:V16QI
> +          (eq:V16QI (match_operand:V16QI 1 "altivec_register_operand" "v")
> +                    (match_operand:V16QI 2 "altivec_register_operand" "v"))))]
> +  "TARGET_P9_VECTOR"
> +  "vcmpneb %0,%1,%2"
> +  [(set_attr "type" "vecsimple")]
> +)
> +
>  ;; Vector Compare Not Equal or Zero Byte
>  (define_insn "vcmpnezb"
>    [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
>         (unspec:V16QI
>          [(match_operand:V16QI 1 "altivec_register_operand" "v")
> @@ -4470,10 +4481,21 @@
>          UNSPEC_VCMPNEH))]
>    "TARGET_P9_VECTOR"
>    "vcmpneh %0,%1,%2"
>    [(set_attr "type" "vecsimple")])
>
> +;; Vector Compare Not Equal Half Word (specified/not+eq:)
> +(define_insn "vcmpneh_spec"
> +  [(set (match_operand:V8HI 0 "altivec_register_operand" "=v")
> +       (not:V8HI
> +         (eq:V8HI (match_operand:V8HI 1 "altivec_register_operand" "v")
> +                  (match_operand:V8HI 2 "altivec_register_operand" "v"))))]
> +  "TARGET_P9_VECTOR"
> +  "vcmpneh %0,%1,%2"
> +  [(set_attr "type" "vecsimple")]
> +)
> +
>  ;; Vector Compare Not Equal or Zero Half Word
>  (define_insn "vcmpnezh"
>    [(set (match_operand:V8HI 0 "altivec_register_operand" "=v")
>         (unspec:V8HI [(match_operand:V8HI 1 "altivec_register_operand" "v")
>                       (match_operand:V8HI 2 "altivec_register_operand" "v")]
> @@ -4491,10 +4513,21 @@
>          UNSPEC_VCMPNEH))]
>    "TARGET_P9_VECTOR"
>    "vcmpnew %0,%1,%2"
>    [(set_attr "type" "vecsimple")])
>
> +;; Vector Compare Not Equal Word (specified/not+eq:)
> +(define_insn "vcmpnew_spec"
> +  [(set (match_operand:V4SI 0 "altivec_register_operand" "=v")
> +       (not:V4SI
> +         (eq:V4SI (match_operand:V4SI 1 "altivec_register_operand" "v")
> +                  (match_operand:V4SI 2 "altivec_register_operand" "v"))))]
> +  "TARGET_P9_VECTOR"
> +  "vcmpnew %0,%1,%2"
> +  [(set_attr "type" "vecsimple")]
> +)
> +
>  ;; Vector Compare Not Equal or Zero Word
>  (define_insn "vcmpnezw"
>    [(set (match_operand:V4SI 0 "altivec_register_operand" "=v")
>         (unspec:V4SI [(match_operand:V4SI 1 "altivec_register_operand" "v")
>                       (match_operand:V4SI 2 "altivec_register_operand" "v")]
> diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c
> index 46a31ae..9dc53da 100644
> --- a/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c
> +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c
> @@ -1,8 +1,8 @@
>  /* { dg-do compile } */
>  /* { dg-require-effective-target powerpc_p9vector_ok } */
> -/* { dg-options "-mcpu=power9" } */
> +/* { dg-options "-mcpu=power9 -O1" } */
>
>  #include <altivec.h>
>
>  vector bool char
>  test_ne_char (vector bool char x, vector bool char y)
> @@ -51,21 +51,22 @@ test_vull_bperm_vull_vuc (vector unsigned long long x,
>
>       test_ne_char              1 vcmpneb
>       test_ne_short             1 vcmpneh
>       test_ne_int               1 vcmpnew
>       test_ne_long              1 vcmpequd, 1 xxlnor inst
> -     test_nabs_long_long       1 xxspltib, 1 vsubudm, 1 vminsd
>       test_neg_long_long        1 vnegd
>       test_vull_bperm_vull_vuc  1 vbpermd
> -
> +     test_nabs_long_long (-O0) 1 xxspltib, 1 vsubudm, 1 vminsd
> +     test_nabs_long_long (-O1) 1 vnegd, vminsd
> +*/
>
>  /* { dg-final { scan-assembler-times "vcmpneb"  1 } } */
>  /* { dg-final { scan-assembler-times "vcmpneh"  1 } } */
>  /* { dg-final { scan-assembler-times "vcmpnew"  1 } } */
>  /* { dg-final { scan-assembler-times "vcmpequd" 1 } } */
>  /* { dg-final { scan-assembler-times "xxlnor"   1 } } */
> -/* { dg-final { scan-assembler-times "xxspltib" 1 } } */
> -/* { dg-final { scan-assembler-times "vsubudm"  1 } } */
> +/* { dg-final { scan-assembler-times "xxspltib" 0 } } */
> +/* { dg-final { scan-assembler-times "vsubudm"  0 } } */
>  /* { dg-final { scan-assembler-times "vminsd"   1 } } */
> -/* { dg-final { scan-assembler-times "vnegd"    1 } } */
> +/* { dg-final { scan-assembler-times "vnegd"    2 } } */
>  /* { dg-final { scan-assembler-times "vbpermd"  1 } } */
>
> diff --git a/gcc/testsuite/gcc.target/powerpc/vec-cmp-sel.c b/gcc/testsuite/gcc.target/powerpc/vec-cmp-sel.c
> index 6f3c093..f74a117 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vec-cmp-sel.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vec-cmp-sel.c
> @@ -10,12 +10,13 @@
>     into
>       c != {0,...,0} ? b : a  */
>
>  #include <altivec.h>
>
> +volatile vector signed long long x = { 25399, -12900 };
> +volatile vector signed long long y = { 12178, -9987 };
> +
>  vector signed long long foo () {
> -  vector signed long long x = { 25399, -12900 };
> -  vector signed long long y = { 12178, -9987 };
>    vector bool long long b = vec_cmpge (x, y);
>    vector signed long long z = vec_sel (y, x, b);
>    return z;
>  }
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-0.c
> index 8e036e3..5c09c70 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-0.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-0.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile { target { powerpc*-*-* } } } */
>  /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
>  /* { dg-require-effective-target powerpc_p9vector_ok } */
> -/* { dg-options "-mcpu=power9" } */
> +/* { dg-options "-mcpu=power9 -O1" } */
>
>  #include <altivec.h>
>
>  vector bool char
>  fetch_data (vector bool char *arg1_p, vector bool char *arg2_p)
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-1.c
> index e510a44..a74f739 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-1.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-1.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile { target { powerpc*-*-* } } } */
>  /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
>  /* { dg-require-effective-target powerpc_p9vector_ok } */
> -/* { dg-options "-mcpu=power9" } */
> +/* { dg-options "-mcpu=power9 -O1" } */
>
>  #include <altivec.h>
>
>  vector bool char
>  fetch_data (vector signed char *arg1_p, vector signed char *arg2_p)
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-2.c
> index 0ea5aa7..f7f1e0d 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-2.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-2.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile { target { powerpc*-*-* } } } */
>  /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
>  /* { dg-require-effective-target powerpc_p9vector_ok } */
> -/* { dg-options "-mcpu=power9" } */
> +/* { dg-options "-mcpu=power9 -O1" } */
>
>  #include <altivec.h>
>
>  vector bool char
>  fetch_data (vector unsigned char *arg1_p, vector unsigned char *arg2_p)
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-3.c
> index 6bb5ebe..8ec94bd 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-3.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-3.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile { target { powerpc*-*-* } } } */
>  /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
>  /* { dg-require-effective-target powerpc_p9vector_ok } */
> -/* { dg-options "-mcpu=power9" } */
> +/* { dg-options "-mcpu=power9 -O1" } */
>
>  #include <altivec.h>
>
>  vector bool short
>  fetch_data (vector signed short *arg1_p, vector signed short *arg2_p)
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-4.c
> index a8d3f17..2f47697 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-4.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-4.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile { target { powerpc*-*-* } } } */
>  /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
>  /* { dg-require-effective-target powerpc_p9vector_ok } */
> -/* { dg-options "-mcpu=power9" } */
> +/* { dg-options "-mcpu=power9 -O1" } */
>
>  #include <altivec.h>
>
>  vector bool short
>  fetch_data (vector unsigned short *arg1_p, vector unsigned short *arg2_p)
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-5.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-5.c
> index dae3e22..1167085 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-5.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-5.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile { target { powerpc*-*-* } } } */
>  /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
>  /* { dg-require-effective-target powerpc_p9vector_ok } */
> -/* { dg-options "-mcpu=power9" } */
> +/* { dg-options "-mcpu=power9 -O1" } */
>
>  #include <altivec.h>
>
>  vector bool int
>  fetch_data (vector signed int *arg1_p, vector signed int *arg2_p)
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-6.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-6.c
> index 550a353..031a48f 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-6.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-6.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile { target { powerpc*-*-* } } } */
>  /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
>  /* { dg-require-effective-target powerpc_p9vector_ok } */
> -/* { dg-options "-mcpu=power9" } */
> +/* { dg-options "-mcpu=power9 -O1" } */
>
>  #include <altivec.h>
>
>  vector bool int
>  fetch_data (vector unsigned int *arg1_p, vector unsigned int *arg2_p)
>
>
Will Schmidt Oct. 13, 2017, 1:34 p.m. | #3
On Thu, 2017-10-12 at 22:05 -0500, Segher Boessenkool wrote:
> > diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
> 
> > +;; Vector Compare Not Equal Byte (specified/not+eq:)
> > +(define_insn "vcmpneb_spec"
> > +  [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
> > +      (not:V16QI
> > +        (eq:V16QI (match_operand:V16QI 1 "altivec_register_operand"
> "v")
> > +                  (match_operand:V16QI 2 "altivec_register_operand"
> "v"))))]
> > +  "TARGET_P9_VECTOR"
> > +  "vcmpneb %0,%1,%2"
> > +  [(set_attr "type" "vecsimple")]
> > +)
> 
> +  [(set_attr "type" "vecsimple")])
> 
> What does "_spec" mean?  That it is not an unspec?  :-)

Yes, exactly. :-)    

> If a name is not (expected to be) used directly, it should start with
> *.

Ok.

> Do we still need the unspec version? 

Not sure..   I'll play with this some more.
Will Schmidt Oct. 13, 2017, 1:36 p.m. | #4
On Fri, 2017-10-13 at 11:36 +0200, Richard Biener wrote:
> On Thu, Oct 12, 2017 at 10:03 PM, Will Schmidt
> <will_schmidt@vnet.ibm.com> wrote:
> > Hi,
> >
> > Add support for gimple folding of vec_cmp_{eq,ge,gt,le,ne} for
> > the integer data types.
> >
> > This adds a handful of entries to the switch statement in builtin_function_type
> > for those builtins having unsigned arguments.
> >
> > Three entries are added to vsx.md to enable vcmpne[bhw] instruction, where we
> > would otherwise generate a vcmpeq + vnor.
> >
> > This patch requires the previously posted "allow integer return type from vector compares" patch.
> >
> > A handful of existing tests required updates to their specified optimization
> > levels to continue to generate the desired code.  builtins-3-p9.c in particular
> > has been updated to reflect improved code gen with the higher specified
> > optimization level.   Testcase coverage is otherwise handled by the already-in-tree
> > gcc.target/powerpc/fold-vec-cmp-*.c tests.
> >
> > Tested OK on P6 and newer. OK for trunk?
> >
> > Thanks,
> > -Will
> >
> > [gcc]
> >
> > 2017-10-12  Will Schmidt  <will_schmidt@vnet.ibm.com>
> >
> >         * config/rs6000/rs6000.c: (rs6000_gimple_fold_builtin) Add support for
> >         folding of vector compares.  (builtin_function_type) Add compare
> >         builtins to the list of functions having unsigned arguments.
> >         * config/rs6000/vsx.md:  Add vcmpne{b,h,w} instructions.
> >
> > [testsuite]
> >
> > 2017-10-12  Will Schmidt  <will_schmidt@vnet.ibm.com>
> >
> >         * gcc.target/powerpc/builtins-3-p9.c: Add -O1, update
> >         expected codegen checks.
> >         * gcc.target/powerpc/vec-cmp-sel.c: Mark vars as volatile.
> >         * gcc.target/powerpc/vsu/vec-cmpne-0.c: Add -O1.
> >         * gcc.target/powerpc/vsu/vec-cmpne-1.c: Add -O1.
> >         * gcc.target/powerpc/vsu/vec-cmpne-2.c: Add -O1.
> >         * gcc.target/powerpc/vsu/vec-cmpne-3.c: Add -O1.
> >         * gcc.target/powerpc/vsu/vec-cmpne-4.c: Add -O1.
> >         * gcc.target/powerpc/vsu/vec-cmpne-5.c: Add -O1.
> >         * gcc.target/powerpc/vsu/vec-cmpne-6.c: Add -O1.
> >
> > diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
> > index 12ddd97..7e73239 100644
> > --- a/gcc/config/rs6000/rs6000.c
> > +++ b/gcc/config/rs6000/rs6000.c
> > @@ -16605,17 +16605,93 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
> >                                            build_int_cst (arg2_type, 0)), arg0);
> >          gimple_set_location (g, loc);
> >          gsi_replace (gsi, g, true);
> >          return true;
> >        }
> > +    /* Vector compares (integer); EQ, NE, GE, GT, LE.  */
> > +    case ALTIVEC_BUILTIN_VCMPEQUB:
> > +    case ALTIVEC_BUILTIN_VCMPEQUH:
> > +    case ALTIVEC_BUILTIN_VCMPEQUW:
> > +    case P8V_BUILTIN_VCMPEQUD:
> > +      {
> > +       arg0 = gimple_call_arg (stmt, 0);
> > +       arg1 = gimple_call_arg (stmt, 1);
> > +       lhs = gimple_call_lhs (stmt);
> > +       gimple *g = gimple_build_assign (lhs, EQ_EXPR, arg0, arg1);
> 
> As said elsewhere this needs to become either
> 
>   tree ctype = build_same_sized_truth_vector_type (TREE_TYPE (lhs));
>   gimple_build_assign (make_ssa_name (ctype), EQ_EXPR, arg0, arg1)
>   gimple_build_assign (lhs, VIEW_CONVERT_EXPR, lhs above);
> 
> (eventually the VCE can be elided - try) or
> 
>   gimple_build_assign (lhs, VEC_COND_EXPR,
>          fold_build2 (EQ_EXPR, ctype, arg0, arg1),
>          vector-with-trues, vector-with-falses);
> 
> depending on what your target can expand.


Alright, i'll work with this some more and see what I come up with.
Thanks for the review and feedback.  :-)

-Will

Patch

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 12ddd97..7e73239 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -16605,17 +16605,93 @@  rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
 					   build_int_cst (arg2_type, 0)), arg0);
 	 gimple_set_location (g, loc);
 	 gsi_replace (gsi, g, true);
 	 return true;
       }
+    /* Vector compares (integer); EQ, NE, GE, GT, LE.  */
+    case ALTIVEC_BUILTIN_VCMPEQUB:
+    case ALTIVEC_BUILTIN_VCMPEQUH:
+    case ALTIVEC_BUILTIN_VCMPEQUW:
+    case P8V_BUILTIN_VCMPEQUD:
+      {
+	arg0 = gimple_call_arg (stmt, 0);
+	arg1 = gimple_call_arg (stmt, 1);
+	lhs = gimple_call_lhs (stmt);
+	gimple *g = gimple_build_assign (lhs, EQ_EXPR, arg0, arg1);
+	gimple_set_location (g, gimple_location (stmt));
+	gsi_replace (gsi, g, true);
+	return true;
+      }
+    case P9V_BUILTIN_CMPNEB:
+    case P9V_BUILTIN_CMPNEH:
+    case P9V_BUILTIN_CMPNEW:
+      {
+	arg0 = gimple_call_arg (stmt, 0);
+	arg1 = gimple_call_arg (stmt, 1);
+	lhs = gimple_call_lhs (stmt);
+	gimple *g = gimple_build_assign (lhs, NE_EXPR, arg0, arg1);
+	gimple_set_location (g, gimple_location (stmt));
+	gsi_replace (gsi, g, true);
+	return true;
+      }
+    case VSX_BUILTIN_CMPGE_16QI:
+    case VSX_BUILTIN_CMPGE_U16QI:
+    case VSX_BUILTIN_CMPGE_8HI:
+    case VSX_BUILTIN_CMPGE_U8HI:
+    case VSX_BUILTIN_CMPGE_4SI:
+    case VSX_BUILTIN_CMPGE_U4SI:
+    case VSX_BUILTIN_CMPGE_2DI:
+    case VSX_BUILTIN_CMPGE_U2DI:
+      {
+	arg0 = gimple_call_arg (stmt, 0);
+	arg1 = gimple_call_arg (stmt, 1);
+	lhs = gimple_call_lhs (stmt);
+	gimple *g = gimple_build_assign (lhs, GE_EXPR, arg0, arg1);
+	gimple_set_location (g, gimple_location (stmt));
+	gsi_replace (gsi, g, true);
+	return true;
+      }
+    case ALTIVEC_BUILTIN_VCMPGTSB:
+    case ALTIVEC_BUILTIN_VCMPGTUH:
+    case ALTIVEC_BUILTIN_VCMPGTSH:
+    case ALTIVEC_BUILTIN_VCMPGTUW:
+    case ALTIVEC_BUILTIN_VCMPGTSW:
+    case ALTIVEC_BUILTIN_VCMPGTUB:
+    case P8V_BUILTIN_VCMPGTUD:
+    case P8V_BUILTIN_VCMPGTSD:
+      {
+	arg0 = gimple_call_arg (stmt, 0);
+	arg1 = gimple_call_arg (stmt, 1);
+	lhs = gimple_call_lhs (stmt);
+	gimple *g = gimple_build_assign (lhs, GT_EXPR, arg0, arg1);
+	gimple_set_location (g, gimple_location (stmt));
+	gsi_replace (gsi, g, true);
+	return true;
+      }
+    case VSX_BUILTIN_CMPLE_16QI:
+    case VSX_BUILTIN_CMPLE_U16QI:
+    case VSX_BUILTIN_CMPLE_8HI:
+    case VSX_BUILTIN_CMPLE_U8HI:
+    case VSX_BUILTIN_CMPLE_4SI:
+    case VSX_BUILTIN_CMPLE_U4SI:
+    case VSX_BUILTIN_CMPLE_2DI:
+    case VSX_BUILTIN_CMPLE_U2DI:
+      {
+	arg0 = gimple_call_arg (stmt, 0);
+	arg1 = gimple_call_arg (stmt, 1);
+	lhs = gimple_call_lhs (stmt);
+	gimple *g = gimple_build_assign (lhs, LE_EXPR, arg0, arg1);
+	gimple_set_location (g, gimple_location (stmt));
+	gsi_replace (gsi, g, true);
+	return true;
+      }
     default:
 	if (TARGET_DEBUG_BUILTIN)
 	   fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n",
 		    fn_code, fn_name1, fn_name2);
       break;
     }
-
   return false;
 }
 
 /* Expand an expression EXP that calls a built-in function,
    with result going to TARGET if that's convenient
@@ -18112,10 +18188,27 @@  builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
     case MISC_BUILTIN_UNPACK_TD:
     case MISC_BUILTIN_UNPACK_V1TI:
       h.uns_p[0] = 1;
       break;
 
+      /* unsigned arguments, bool return (compares).  */
+    case ALTIVEC_BUILTIN_VCMPEQUB:
+    case ALTIVEC_BUILTIN_VCMPEQUH:
+    case ALTIVEC_BUILTIN_VCMPEQUW:
+    case P8V_BUILTIN_VCMPEQUD:
+    case VSX_BUILTIN_CMPGE_U16QI:
+    case VSX_BUILTIN_CMPGE_U8HI:
+    case VSX_BUILTIN_CMPGE_U4SI:
+    case VSX_BUILTIN_CMPGE_U2DI:
+    case ALTIVEC_BUILTIN_VCMPGTUB:
+    case ALTIVEC_BUILTIN_VCMPGTUH:
+    case ALTIVEC_BUILTIN_VCMPGTUW:
+    case P8V_BUILTIN_VCMPGTUD:
+      h.uns_p[1]=1;
+      h.uns_p[2]=1;
+      break;
+
       /* unsigned arguments for 128-bit pack instructions.  */
     case MISC_BUILTIN_PACK_TD:
     case MISC_BUILTIN_PACK_V1TI:
       h.uns_p[1] = 1;
       h.uns_p[2] = 1;
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 35be5de..baf05ca 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4449,10 +4449,21 @@ 
 	 UNSPEC_VCMPNEB))]
   "TARGET_P9_VECTOR"
   "vcmpneb %0,%1,%2"
   [(set_attr "type" "vecsimple")])
 
+;; Vector Compare Not Equal Byte (specified/not+eq:)
+(define_insn "vcmpneb_spec"
+  [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
+	 (not:V16QI
+	   (eq:V16QI (match_operand:V16QI 1 "altivec_register_operand" "v")
+		     (match_operand:V16QI 2 "altivec_register_operand" "v"))))]
+  "TARGET_P9_VECTOR"
+  "vcmpneb %0,%1,%2"
+  [(set_attr "type" "vecsimple")]
+)
+
 ;; Vector Compare Not Equal or Zero Byte
 (define_insn "vcmpnezb"
   [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
 	(unspec:V16QI
 	 [(match_operand:V16QI 1 "altivec_register_operand" "v")
@@ -4470,10 +4481,21 @@ 
 	 UNSPEC_VCMPNEH))]
   "TARGET_P9_VECTOR"
   "vcmpneh %0,%1,%2"
   [(set_attr "type" "vecsimple")])
 
+;; Vector Compare Not Equal Half Word (specified/not+eq:)
+(define_insn "vcmpneh_spec"
+  [(set (match_operand:V8HI 0 "altivec_register_operand" "=v")
+	(not:V8HI
+	  (eq:V8HI (match_operand:V8HI 1 "altivec_register_operand" "v")
+		   (match_operand:V8HI 2 "altivec_register_operand" "v"))))]
+  "TARGET_P9_VECTOR"
+  "vcmpneh %0,%1,%2"
+  [(set_attr "type" "vecsimple")]
+)
+
 ;; Vector Compare Not Equal or Zero Half Word
 (define_insn "vcmpnezh"
   [(set (match_operand:V8HI 0 "altivec_register_operand" "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "altivec_register_operand" "v")
 		      (match_operand:V8HI 2 "altivec_register_operand" "v")]
@@ -4491,10 +4513,21 @@ 
 	 UNSPEC_VCMPNEH))]
   "TARGET_P9_VECTOR"
   "vcmpnew %0,%1,%2"
   [(set_attr "type" "vecsimple")])
 
+;; Vector Compare Not Equal Word (specified/not+eq:)
+(define_insn "vcmpnew_spec"
+  [(set (match_operand:V4SI 0 "altivec_register_operand" "=v")
+	(not:V4SI
+	  (eq:V4SI (match_operand:V4SI 1 "altivec_register_operand" "v")
+		   (match_operand:V4SI 2 "altivec_register_operand" "v"))))]
+  "TARGET_P9_VECTOR"
+  "vcmpnew %0,%1,%2"
+  [(set_attr "type" "vecsimple")]
+)
+
 ;; Vector Compare Not Equal or Zero Word
 (define_insn "vcmpnezw"
   [(set (match_operand:V4SI 0 "altivec_register_operand" "=v")
 	(unspec:V4SI [(match_operand:V4SI 1 "altivec_register_operand" "v")
 		      (match_operand:V4SI 2 "altivec_register_operand" "v")]
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c
index 46a31ae..9dc53da 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c
@@ -1,8 +1,8 @@ 
 /* { dg-do compile } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9" } */
+/* { dg-options "-mcpu=power9 -O1" } */
 
 #include <altivec.h>
 
 vector bool char
 test_ne_char (vector bool char x, vector bool char y)
@@ -51,21 +51,22 @@  test_vull_bperm_vull_vuc (vector unsigned long long x,
 
      test_ne_char              1 vcmpneb
      test_ne_short             1 vcmpneh
      test_ne_int               1 vcmpnew
      test_ne_long              1 vcmpequd, 1 xxlnor inst
-     test_nabs_long_long       1 xxspltib, 1 vsubudm, 1 vminsd
      test_neg_long_long        1 vnegd
      test_vull_bperm_vull_vuc  1 vbpermd
-
+     test_nabs_long_long (-O0) 1 xxspltib, 1 vsubudm, 1 vminsd
+     test_nabs_long_long (-O1) 1 vnegd, vminsd
+*/
 
 /* { dg-final { scan-assembler-times "vcmpneb"  1 } } */
 /* { dg-final { scan-assembler-times "vcmpneh"  1 } } */
 /* { dg-final { scan-assembler-times "vcmpnew"  1 } } */
 /* { dg-final { scan-assembler-times "vcmpequd" 1 } } */
 /* { dg-final { scan-assembler-times "xxlnor"   1 } } */
-/* { dg-final { scan-assembler-times "xxspltib" 1 } } */
-/* { dg-final { scan-assembler-times "vsubudm"  1 } } */
+/* { dg-final { scan-assembler-times "xxspltib" 0 } } */
+/* { dg-final { scan-assembler-times "vsubudm"  0 } } */
 /* { dg-final { scan-assembler-times "vminsd"   1 } } */
-/* { dg-final { scan-assembler-times "vnegd"    1 } } */
+/* { dg-final { scan-assembler-times "vnegd"    2 } } */
 /* { dg-final { scan-assembler-times "vbpermd"  1 } } */
 
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-cmp-sel.c b/gcc/testsuite/gcc.target/powerpc/vec-cmp-sel.c
index 6f3c093..f74a117 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-cmp-sel.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-cmp-sel.c
@@ -10,12 +10,13 @@ 
    into
      c != {0,...,0} ? b : a  */
 
 #include <altivec.h>
 
+volatile vector signed long long x = { 25399, -12900 };
+volatile vector signed long long y = { 12178, -9987 };
+
 vector signed long long foo () {
-  vector signed long long x = { 25399, -12900 };
-  vector signed long long y = { 12178, -9987 };
   vector bool long long b = vec_cmpge (x, y);
   vector signed long long z = vec_sel (y, x, b);
   return z;
 }
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-0.c
index 8e036e3..5c09c70 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-0.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-0.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile { target { powerpc*-*-* } } } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9" } */
+/* { dg-options "-mcpu=power9 -O1" } */
 
 #include <altivec.h>
 
 vector bool char
 fetch_data (vector bool char *arg1_p, vector bool char *arg2_p)
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-1.c
index e510a44..a74f739 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-1.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile { target { powerpc*-*-* } } } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9" } */
+/* { dg-options "-mcpu=power9 -O1" } */
 
 #include <altivec.h>
 
 vector bool char
 fetch_data (vector signed char *arg1_p, vector signed char *arg2_p)
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-2.c
index 0ea5aa7..f7f1e0d 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-2.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile { target { powerpc*-*-* } } } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9" } */
+/* { dg-options "-mcpu=power9 -O1" } */
 
 #include <altivec.h>
 
 vector bool char
 fetch_data (vector unsigned char *arg1_p, vector unsigned char *arg2_p)
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-3.c
index 6bb5ebe..8ec94bd 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-3.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile { target { powerpc*-*-* } } } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9" } */
+/* { dg-options "-mcpu=power9 -O1" } */
 
 #include <altivec.h>
 
 vector bool short
 fetch_data (vector signed short *arg1_p, vector signed short *arg2_p)
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-4.c
index a8d3f17..2f47697 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-4.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile { target { powerpc*-*-* } } } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9" } */
+/* { dg-options "-mcpu=power9 -O1" } */
 
 #include <altivec.h>
 
 vector bool short
 fetch_data (vector unsigned short *arg1_p, vector unsigned short *arg2_p)
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-5.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-5.c
index dae3e22..1167085 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-5.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-5.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile { target { powerpc*-*-* } } } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9" } */
+/* { dg-options "-mcpu=power9 -O1" } */
 
 #include <altivec.h>
 
 vector bool int
 fetch_data (vector signed int *arg1_p, vector signed int *arg2_p)
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-6.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-6.c
index 550a353..031a48f 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-6.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-6.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile { target { powerpc*-*-* } } } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9" } */
+/* { dg-options "-mcpu=power9 -O1" } */
 
 #include <altivec.h>
 
 vector bool int
 fetch_data (vector unsigned int *arg1_p, vector unsigned int *arg2_p)