[U-Boot] armv8: ls1088aqds: Change phy mode to PHY_INTERFACE_MODE_RGMII_ID

Message ID 1507801914-25968-1-git-send-email-Ashish.Kumar@nxp.com
State Accepted
Delegated to: York Sun
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  • [U-Boot] armv8: ls1088aqds: Change phy mode to PHY_INTERFACE_MODE_RGMII_ID
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Commit Message

Ashish Kumar Oct. 12, 2017, 9:51 a.m.
Since TX delay is now enabled only in PHY_INTERFACE_MODE_RGMII_ID
PHY_INTERFACE_MODE_RGMII_TXID.

These change where introduced in phy driver in commit titled
"net: phy: realtek: fix enabling of the TX-delay for RTL8211F"

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
---
 board/freescale/ls1088a/eth_ls1088aqds.c | 1 +
 drivers/net/ldpaa_eth/ls1088a.c          | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

Comments

York Sun Oct. 30, 2017, 6:33 p.m. | #1
On 10/12/2017 02:51 AM, Ashish Kumar wrote:
> Since TX delay is now enabled only in PHY_INTERFACE_MODE_RGMII_ID
> PHY_INTERFACE_MODE_RGMII_TXID.
> 
> These change where introduced in phy driver in commit titled
> "net: phy: realtek: fix enabling of the TX-delay for RTL8211F"
> 
> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
> ---

Minor change to commit message.
Applied to fsl-qoriq master. Thanks.

York

Patch

diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c
index f5320eb..f056fde 100644
--- a/board/freescale/ls1088a/eth_ls1088aqds.c
+++ b/board/freescale/ls1088a/eth_ls1088aqds.c
@@ -637,6 +637,7 @@  int board_eth_init(bd_t *bis)
 	for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
 		switch (wriop_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			ls1088a_handle_phy_interface_rgmii(i);
 			break;
 		case PHY_INTERFACE_MODE_QSGMII:
diff --git a/drivers/net/ldpaa_eth/ls1088a.c b/drivers/net/ldpaa_eth/ls1088a.c
index 061935e..780a239 100644
--- a/drivers/net/ldpaa_eth/ls1088a.c
+++ b/drivers/net/ldpaa_eth/ls1088a.c
@@ -99,7 +99,7 @@  void fsl_rgmii_init(void)
 	ec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT;
 
 	if (!ec)
-		wriop_init_dpmac_enet_if(4, PHY_INTERFACE_MODE_RGMII);
+		wriop_init_dpmac_enet_if(4, PHY_INTERFACE_MODE_RGMII_ID);
 #endif
 
 #ifdef CONFIG_SYS_FSL_EC2
@@ -108,7 +108,7 @@  void fsl_rgmii_init(void)
 	ec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT;
 
 	if (!ec)
-		wriop_init_dpmac_enet_if(5, PHY_INTERFACE_MODE_RGMII);
+		wriop_init_dpmac_enet_if(5, PHY_INTERFACE_MODE_RGMII_ID);
 #endif
 }
 #endif