From patchwork Wed Oct 11 22:34:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 824604 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.infradead.org (client-ip=65.50.211.133; helo=bombadil.infradead.org; envelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Z1/toLHm"; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yC83h4YsZz9t2S for ; Thu, 12 Oct 2017 09:36:48 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=m3S1sAM3WC2WSULokSHavyOROfr/ffKn4LJkVrfT4XQ=; b=Z1/toLHmqp+A6j zHub711+Gq9st53IRKcncfotO1sEdEiK8Mjdj1D8rZKvcuel5VL4knlK7L5DbB9crP+9trV923Q+W jnApBPPWNyNVgP8w4y02BYZ6kFJZjcvmuKQfHGwWheUhAky29to9qycB7d90gQ+jCwVo3xUhJi8Wh btk98UJCvYbRzi6qzSOdZ2Xg5B7N2JaoVoVysywfscxirORMXQU0Ok1osDUNUwWqltK1RcK4xfS3t BRg3tcGS/pHmGQdBmyPhwb12Z7OfM2dqBjSCOaELuGDn2y5SNZ5Je4sfgdFX5evysA3Fq1c2dur3+ 0gqmKfzV7AJ3NnTRSwvw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1e2PcI-0004wa-J1; Wed, 11 Oct 2017 22:36:42 +0000 Received: from rnd-relay.smtp.broadcom.com ([192.19.229.170]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1e2Pap-0002JV-Md for linux-arm-kernel@lists.infradead.org; Wed, 11 Oct 2017 22:35:16 +0000 Received: from mail-irv-17.broadcom.com (mail-irv-17.lvn.broadcom.net [10.75.224.233]) by rnd-relay.smtp.broadcom.com (Postfix) with ESMTP id DB94D30C039; Wed, 11 Oct 2017 15:34:49 -0700 (PDT) Received: from stbsrv-and-3.and.broadcom.com (stbsrv-and-3.and.broadcom.com [10.28.16.21]) by mail-irv-17.broadcom.com (Postfix) with ESMTP id A10AC81EB3; Wed, 11 Oct 2017 15:34:47 -0700 (PDT) From: Jim Quinlan To: linux-kernel@vger.kernel.org Subject: [PATCH 1/9] SOC: brcmstb: add memory API Date: Wed, 11 Oct 2017 18:34:21 -0400 Message-Id: <1507761269-7017-2-git-send-email-jim2101024@gmail.com> X-Mailer: git-send-email 1.9.0.138.g2de3478 In-Reply-To: <1507761269-7017-1-git-send-email-jim2101024@gmail.com> References: <1507761269-7017-1-git-send-email-jim2101024@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171011_153511_842519_FAA6F433 X-CRM114-Status: GOOD ( 22.85 ) X-Spam-Score: -2.4 (--) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-2.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [192.19.229.170 listed in list.dnswl.org] 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit (jim2101024[at]gmail.com) 0.0 DKIM_ADSP_CUSTOM_MED No valid author signature, adsp_override is CUSTOM_MED 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (jim2101024[at]gmail.com) 0.7 SPF_SOFTFAIL SPF: sender does not match SPF record (softfail) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.9 NML_ADSP_CUSTOM_MED ADSP custom_med hit, and not from a mailing list X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , linux-mips@linux-mips.org, Florian Fainelli , devicetree@vger.kernel.org, linux-pci@vger.kernel.org, Kevin Cernekee , Will Deacon , Ralf Baechle , Rob Herring , bcm-kernel-feedback-list@broadcom.com, Gregory Fong , Catalin Marinas , Bjorn Helgaas , Jim Quinlan , Brian Norris , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org From: Florian Fainelli This commit adds a memory API suitable for ascertaining the sizes of each of the N memory controllers in a Broadcom STB chip. Its first user will be the Broadcom STB PCIe root complex driver, which needs to know these sizes to properly set up DMA mappings for inbound regions. We cannot use memblock here or anything like what Linux provides because it collapses adjacent regions within a larger block, and here we actually need per-memory controller addresses and sizes, which is why we resort to manual DT parsing. Signed-off-by: Jim Quinlan --- drivers/soc/bcm/brcmstb/Makefile | 2 +- drivers/soc/bcm/brcmstb/memory.c | 183 +++++++++++++++++++++++++++++++++++++++ include/soc/brcmstb/memory_api.h | 25 ++++++ 3 files changed, 209 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/bcm/brcmstb/memory.c create mode 100644 include/soc/brcmstb/memory_api.h diff --git a/drivers/soc/bcm/brcmstb/Makefile b/drivers/soc/bcm/brcmstb/Makefile index 9120b27..4cea7b6 100644 --- a/drivers/soc/bcm/brcmstb/Makefile +++ b/drivers/soc/bcm/brcmstb/Makefile @@ -1 +1 @@ -obj-y += common.o biuctrl.o +obj-y += common.o biuctrl.o memory.o diff --git a/drivers/soc/bcm/brcmstb/memory.c b/drivers/soc/bcm/brcmstb/memory.c new file mode 100644 index 0000000..cb6bf73 --- /dev/null +++ b/drivers/soc/bcm/brcmstb/memory.c @@ -0,0 +1,183 @@ +/* + * Copyright © 2015-2017 Broadcom + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * A copy of the GPL is available at + * http://www.broadcom.com/licenses/GPLv2.php or from the Free Software + * Foundation at https://www.gnu.org/licenses/ . + */ + +#include +#include +#include +#include +#include +#include +#include + +/* -------------------- Constants -------------------- */ + +/* Macros to help extract property data */ +#define U8TOU32(b, offs) \ + ((((u32)b[0 + offs] << 0) & 0x000000ff) | \ + (((u32)b[1 + offs] << 8) & 0x0000ff00) | \ + (((u32)b[2 + offs] << 16) & 0x00ff0000) | \ + (((u32)b[3 + offs] << 24) & 0xff000000)) + +#define DT_PROP_DATA_TO_U32(b, offs) (fdt32_to_cpu(U8TOU32(b, offs))) + +/* Constants used when retrieving memc info */ +#define NUM_BUS_RANGES 10 +#define BUS_RANGE_ULIMIT_SHIFT 4 +#define BUS_RANGE_LLIMIT_SHIFT 4 +#define BUS_RANGE_PA_SHIFT 12 + +enum { + BUSNUM_MCP0 = 0x4, + BUSNUM_MCP1 = 0x5, + BUSNUM_MCP2 = 0x6, +}; + +/* -------------------- Functions -------------------- */ + +/* + * If the DT nodes are handy, determine which MEMC holds the specified + * physical address. + */ +#ifdef CONFIG_ARCH_BRCMSTB +int __brcmstb_memory_phys_addr_to_memc(phys_addr_t pa, void __iomem *base) +{ + int memc = -1; + int i; + + for (i = 0; i < NUM_BUS_RANGES; i++, base += 8) { + const u64 ulimit_raw = readl(base); + const u64 llimit_raw = readl(base + 4); + const u64 ulimit = + ((ulimit_raw >> BUS_RANGE_ULIMIT_SHIFT) + << BUS_RANGE_PA_SHIFT) | 0xfff; + const u64 llimit = (llimit_raw >> BUS_RANGE_LLIMIT_SHIFT) + << BUS_RANGE_PA_SHIFT; + const u32 busnum = (u32)(ulimit_raw & 0xf); + + if (pa >= llimit && pa <= ulimit) { + if (busnum >= BUSNUM_MCP0 && busnum <= BUSNUM_MCP2) { + memc = busnum - BUSNUM_MCP0; + break; + } + } + } + + return memc; +} + +int brcmstb_memory_phys_addr_to_memc(phys_addr_t pa) +{ + int memc = -1; + struct device_node *np; + void __iomem *cpubiuctrl; + + np = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl"); + if (!np) + return memc; + + cpubiuctrl = of_iomap(np, 0); + if (!cpubiuctrl) + goto cleanup; + + memc = __brcmstb_memory_phys_addr_to_memc(pa, cpubiuctrl); + iounmap(cpubiuctrl); + +cleanup: + of_node_put(np); + + return memc; +} + +#elif defined(CONFIG_MIPS) +int brcmstb_memory_phys_addr_to_memc(phys_addr_t pa) +{ + /* The logic here is fairly simple and hardcoded: if pa <= 0x5000_0000, + * then this is MEMC0, else MEMC1. + * + * For systems with 2GB on MEMC0, MEMC1 starts at 9000_0000, with 1GB + * on MEMC0, MEMC1 starts at 6000_0000. + */ + if (pa >= 0x50000000ULL) + return 1; + else + return 0; +} +#endif +EXPORT_SYMBOL(brcmstb_memory_phys_addr_to_memc); + +u64 brcmstb_memory_memc_size(int memc) +{ + const void *fdt = initial_boot_params; + const int mem_offset = fdt_path_offset(fdt, "/memory"); + int addr_cells = 1, size_cells = 1; + const struct fdt_property *prop; + int proplen, cellslen; + u64 memc_size = 0; + int i; + + /* Get root size and address cells if specified */ + prop = fdt_get_property(fdt, 0, "#size-cells", &proplen); + if (prop) + size_cells = DT_PROP_DATA_TO_U32(prop->data, 0); + + prop = fdt_get_property(fdt, 0, "#address-cells", &proplen); + if (prop) + addr_cells = DT_PROP_DATA_TO_U32(prop->data, 0); + + if (mem_offset < 0) + return -1; + + prop = fdt_get_property(fdt, mem_offset, "reg", &proplen); + cellslen = (int)sizeof(u32) * (addr_cells + size_cells); + if ((proplen % cellslen) != 0) + return -1; + + for (i = 0; i < proplen / cellslen; ++i) { + u64 addr = 0; + u64 size = 0; + int memc_idx; + int j; + + for (j = 0; j < addr_cells; ++j) { + int offset = (cellslen * i) + (sizeof(u32) * j); + + addr |= (u64)DT_PROP_DATA_TO_U32(prop->data, offset) << + ((addr_cells - j - 1) * 32); + } + for (j = 0; j < size_cells; ++j) { + int offset = (cellslen * i) + + (sizeof(u32) * (j + addr_cells)); + + size |= (u64)DT_PROP_DATA_TO_U32(prop->data, offset) << + ((size_cells - j - 1) * 32); + } + + if ((phys_addr_t)addr != addr) { + pr_err("phys_addr_t is smaller than provided address 0x%llx!\n", + addr); + return -1; + } + + memc_idx = brcmstb_memory_phys_addr_to_memc((phys_addr_t)addr); + if (memc_idx == memc) + memc_size += size; + } + + return memc_size; +} +EXPORT_SYMBOL(brcmstb_memory_memc_size); + diff --git a/include/soc/brcmstb/memory_api.h b/include/soc/brcmstb/memory_api.h new file mode 100644 index 0000000..d922906 --- /dev/null +++ b/include/soc/brcmstb/memory_api.h @@ -0,0 +1,25 @@ +#ifndef __MEMORY_API_H +#define __MEMORY_API_H + +/* + * Bus Interface Unit control register setup, must happen early during boot, + * before SMP is brought up, called by machine entry point. + */ +void brcmstb_biuctrl_init(void); + +#ifdef CONFIG_SOC_BRCMSTB +int brcmstb_memory_phys_addr_to_memc(phys_addr_t pa); +u64 brcmstb_memory_memc_size(int memc); +#else +static inline int brcmstb_memory_phys_addr_to_memc(phys_addr_t pa) +{ + return -EINVAL; +} + +static inline u64 brcmstb_memory_memc_size(int memc) +{ + return -1; +} +#endif + +#endif /* __MEMORY_API_H */