Patchwork [v2] target-arm: fix VSHLL Neon instruction.

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Submitter Christophe LYON
Date Feb. 9, 2011, 12:19 p.m.
Message ID <4D528643.4080106@st.com>
Download mbox | patch
Permalink /patch/82454/
State New
Headers show

Comments

Christophe LYON - Feb. 9, 2011, 12:19 p.m.
Fix bit mask used when widening the result of shift on narrow input.

Signed-off-by: Christophe Lyon <christophe.lyon@st.com>
---
 target-arm/translate.c |   18 +++++++++++++++---
 1 files changed, 15 insertions(+), 3 deletions(-)
Peter Maydell - Feb. 9, 2011, 2:23 p.m.
On 9 February 2011 12:19, Christophe Lyon <christophe.lyon@st.com> wrote:
>
> Fix bit mask used when widening the result of shift on narrow input.
>
> Signed-off-by: Christophe Lyon <christophe.lyon@st.com>

Confirmed with random instruction testing that this patch fixes VSHLL.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Aurelien Jarno - Feb. 9, 2011, 6:48 p.m.
On Wed, Feb 09, 2011 at 02:23:24PM +0000, Peter Maydell wrote:
> On 9 February 2011 12:19, Christophe Lyon <christophe.lyon@st.com> wrote:
> >
> > Fix bit mask used when widening the result of shift on narrow input.
> >
> > Signed-off-by: Christophe Lyon <christophe.lyon@st.com>
> 
> Confirmed with random instruction testing that this patch fixes VSHLL.
> 
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> 

Thanks, applied.

Patch

diff --git a/target-arm/translate.c b/target-arm/translate.c
index b694eed..16c61f1 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -4882,16 +4882,28 @@  static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
                         /* The shift is less than the width of the source
                            type, so we can just shift the whole register.  */
                         tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
+                        /* Widen the result of shift: we need to clear
+                         * the potential overflow bits resulting from
+                         * left bits of the narrow input appearing as
+                         * right bits of left the neighbour narrow
+                         * input.  */
                         if (size < 2 || !u) {
                             uint64_t imm64;
                             if (size == 0) {
                                 imm = (0xffu >> (8 - shift));
                                 imm |= imm << 16;
-                            } else {
+                            } else if (size == 1) {
                                 imm = 0xffff >> (16 - shift);
+                            } else {
+                                /* size == 2 */
+                                imm = 0xffffffff >> (32 - shift);
+                            }
+                            if (size < 2) {
+                                imm64 = imm | (((uint64_t)imm) << 32);
+                            } else {
+                                imm64 = imm;
                             }
-                            imm64 = imm | (((uint64_t)imm) << 32);
-                            tcg_gen_andi_i64(cpu_V0, cpu_V0, imm64);
+                            tcg_gen_andi_i64(cpu_V0, cpu_V0, ~imm64);
                         }
                     }
                     neon_store_reg64(cpu_V0, rd + pass);