[rs6000] testcase coverage for vec_splat_uX

Message ID 1507580306.26707.139.camel@brimstone.rchland.ibm.com
State New
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  • [rs6000] testcase coverage for vec_splat_uX
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Commit Message

Will Schmidt Oct. 9, 2017, 8:18 p.m.
Hi, 
  
Add testcase coverage for vec_splat_{u8,s8,u16,s16,u32,s32} built-ins.

Tested on P6 and newer.   OK for trunk? 

Thanks, 
-Will

    
[testsuite]

|-------* gcc.target/powerpc/fold-vec-splat-16.c: New
|-------* gcc.target/powerpc/fold-vec-splat-32.c: New.
|-------* gcc.target/powerpc/fold-vec-splat-8.c: New.

Comments

Segher Boessenkool Oct. 9, 2017, 9:45 p.m. | #1
On Mon, Oct 09, 2017 at 03:18:26PM -0500, Will Schmidt wrote:
> Add testcase coverage for vec_splat_{u8,s8,u16,s16,u32,s32} built-ins.

> [testsuite]
> 
> |-------* gcc.target/powerpc/fold-vec-splat-16.c: New
> |-------* gcc.target/powerpc/fold-vec-splat-32.c: New.
> |-------* gcc.target/powerpc/fold-vec-splat-8.c: New.

That look fine, please commit.  Thanks!


Segher

Patch

diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-16.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-16.c
new file mode 100644
index 0000000..bb4a8d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-16.c
@@ -0,0 +1,46 @@ 
+/* Verify that overloaded built-ins for vec_splat with int
+   inputs produce the right code.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx -O2" } */
+
+#include <altivec.h>
+
+vector signed short
+testss_1 ()
+{
+  return vec_splat_s16 (5);
+}
+
+vector signed short
+testss_2 ()
+{
+  return vec_splat_s16 (-5);
+}
+
+vector signed short
+testss_3 ()
+{
+  return vec_splat_s16 (15);
+}
+
+vector unsigned short
+testus_1 ()
+{
+  return vec_splat_u16 (5);
+}
+
+vector unsigned short
+testus_2 ()
+{
+  return vec_splat_u16 (-5);
+}
+
+vector unsigned short
+testus_3 ()
+{
+  return vec_splat_u16 (15);
+}
+
+/* { dg-final { scan-assembler-times "vspltish" 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-32.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-32.c
new file mode 100644
index 0000000..f59849e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-32.c
@@ -0,0 +1,46 @@ 
+/* Verify that overloaded built-ins for vec_splat with int
+   inputs produce the right code.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector signed int
+testsi_1 ()
+{
+  return vec_splat_s32 (5);
+}
+
+vector signed int
+testsi_2 ()
+{
+  return vec_splat_s32 (-5);
+}
+
+vector signed int
+testsi_3 ()
+{
+ return vec_splat_s32 (15);
+}
+
+vector unsigned int
+testui_1 ()
+{
+  return vec_splat_u32 (5);
+}
+
+vector unsigned int
+testui_2 ()
+{
+  return vec_splat_u32 (-5);
+}
+
+vector unsigned int
+testui_3 ()
+{
+  return vec_splat_u32 (15);
+}
+
+/* { dg-final { scan-assembler-times "vspltisw" 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-8.c
new file mode 100644
index 0000000..679fcb3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-8.c
@@ -0,0 +1,46 @@ 
+/* Verify that overloaded built-ins for vec_splat with int
+   inputs produce the right code.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector signed char
+testsc_1 ()
+{
+  return vec_splat_s8 (5);
+}
+
+vector signed char
+testsc_2 ()
+{
+  return vec_splat_s8 (-5);
+}
+
+vector signed char
+testsc_3 ()
+{
+  return vec_splat_s8 (15);
+}
+
+vector unsigned char
+testuc_1 ()
+{
+  return vec_splat_u8 (5);
+}
+
+vector unsigned char
+testuc_2 ()
+{
+  return vec_splat_u8 (-5);
+}
+
+vector unsigned char
+testuc_3 ()
+{
+  return vec_splat_u8 (15);
+}
+
+/* { dg-final { scan-assembler-times "vspltisb" 6 } } */