From patchwork Tue Feb 8 12:24:54 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartlomiej Zolnierkiewicz X-Patchwork-Id: 82317 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 9985AB6F07 for ; Tue, 8 Feb 2011 23:27:57 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753948Ab1BHMZH (ORCPT ); Tue, 8 Feb 2011 07:25:07 -0500 Received: from mail-ew0-f46.google.com ([209.85.215.46]:61026 "EHLO mail-ew0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753917Ab1BHMZE (ORCPT ); Tue, 8 Feb 2011 07:25:04 -0500 Received: by mail-ew0-f46.google.com with SMTP id 5so2881584ewy.19 for ; Tue, 08 Feb 2011 04:25:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:cc:date:message-id:in-reply-to :references:subject; bh=8rW3HkveOcUBLyKsTA5W8BL8zhapVyooWt26YzuF9Ac=; b=i/ehlrM6fNqXahM8Kk+DDRsBYAG+KTd+19VQ0G1t3X9IgIFfhrWY9+Igrdz3HmS0OV INeNbd6POiUMYjefzpvCtwlPz3DEcWdBP7E/6OPZAHCknHh129XCYCWapU8M58gr/StX 7K/0XCILBa3m+9/yc/CpSH4eTH44tblJZ2lSw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:date:message-id:in-reply-to:references:subject; b=Ov/GkNeXzk1pNNy9b1gdeaRzRDYp6rNKLRO+aDuahZca3zLjNW6tx898de7amC2L2D Ih5kPnd7U6T0sXd6Htnq8SNImPBc7feKzO8TBq7buFiaa7eMGAE/PV2SEQb/JSW+pPgk iNe5vlIjoF/O+pHmLbJ7FxGdiV6RZGW46K0Do= Received: by 10.213.7.67 with SMTP id c3mr20827854ebc.68.1297167903709; Tue, 08 Feb 2011 04:25:03 -0800 (PST) Received: from linux-mhg7.site (89-74-121-163.dynamic.chello.pl [89.74.121.163]) by mx.google.com with ESMTPS id t5sm3960582eeh.20.2011.02.08.04.25.01 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 08 Feb 2011 04:25:02 -0800 (PST) From: Bartlomiej Zolnierkiewicz To: linux-ide@vger.kernel.org Cc: Bartlomiej Zolnierkiewicz , linux-kernel@vger.kernel.org Date: Tue, 08 Feb 2011 13:24:54 +0100 Message-Id: <20110208122454.19110.4318.sendpatchset@linux-mhg7.site> In-Reply-To: <20110208122314.19110.4092.sendpatchset@linux-mhg7.site> References: <20110208122314.19110.4092.sendpatchset@linux-mhg7.site> Subject: [PATCH 11/20] pata_rdc: unify code for programming PIO and MWDMA timings Sender: linux-ide-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org From 0bde1b0fa0d0f05659c147a204d3e4d16c05c276 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Tue, 8 Feb 2011 12:39:27 +0100 Subject: [PATCH 11/20] pata_rdc: unify code for programming PIO and MWDMA timings Besides making things noticably simpler it results in ~8% decrease in the driver LOC count and also ~8% decrease in the driver binary size (as measured on x86-32). Fix rdc_set_piomode() documentation while at it. Signed-off-by: Bartlomiej Zolnierkiewicz --- drivers/ata/pata_rdc.c | 99 ++++++++++++++++-------------------------------- 1 files changed, 33 insertions(+), 66 deletions(-) diff --git a/drivers/ata/pata_rdc.c b/drivers/ata/pata_rdc.c index 5fbe9b1..d32b252 100644 --- a/drivers/ata/pata_rdc.c +++ b/drivers/ata/pata_rdc.c @@ -86,20 +86,9 @@ static int rdc_pata_prereset(struct ata_link *link, unsigned long deadline) return ata_sff_prereset(link, deadline); } -/** - * rdc_set_piomode - Initialize host controller PATA PIO timings - * @ap: Port whose timings we are configuring - * @adev: um - * - * Set PIO mode for device, in host controller PCI config space. - * - * LOCKING: - * None (inherited from caller). - */ - -static void rdc_set_piomode(struct ata_port *ap, struct ata_device *adev) +static void rdc_set_timings(struct ata_port *ap, struct ata_device *adev, + u8 pio, bool use_mwdma) { - unsigned int pio = adev->pio_mode - XFER_PIO_0; struct pci_dev *dev = to_pci_dev(ap->host->dev); unsigned int is_slave = (adev->devno != 0); unsigned int master_port= ap->port_no ? 0x42 : 0x40; @@ -116,13 +105,17 @@ static void rdc_set_piomode(struct ata_port *ap, struct ata_device *adev) { 2, 1 }, { 2, 3 }, }; - if (pio >= 2) + if (pio >= 2 || use_mwdma) control |= 1; /* TIME1 enable */ - if (ata_pio_need_iordy(adev)) + if (ata_pio_need_iordy(adev) || use_mwdma) control |= 2; /* IE enable */ - if (adev->class == ATA_DEV_ATA) control |= 4; /* PPE enable */ + /* If the drive MWDMA is faster than it can do PIO then + we must force PIO into PIO0 */ + if (use_mwdma && adev->pio_mode < (XFER_PIO_0 + pio)) + /* Enable DMA timing only */ + control |= 8; /* PIO cycles in PIO0 */ /* PIO configuration clears DTE unconditionally. It will be * programmed in set_dmamode which is guaranteed to be called @@ -164,6 +157,22 @@ static void rdc_set_piomode(struct ata_port *ap, struct ata_device *adev) } /** + * rdc_set_piomode - Initialize host controller PATA PIO timings + * @ap: Port whose timings we are configuring + * @adev: Drive in question + * + * Set PIO mode for device, in host controller PCI config space. + * + * LOCKING: + * None (inherited from caller). + */ + +static void rdc_set_piomode(struct ata_port *ap, struct ata_device *adev) +{ + rdc_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0, 0); +} + +/** * rdc_set_dmamode - Initialize host controller PATA PIO timings * @ap: Port whose timings we are configuring * @adev: Drive in question @@ -177,28 +186,18 @@ static void rdc_set_piomode(struct ata_port *ap, struct ata_device *adev) static void rdc_set_dmamode(struct ata_port *ap, struct ata_device *adev) { struct pci_dev *dev = to_pci_dev(ap->host->dev); - u8 master_port = ap->port_no ? 0x42 : 0x40; - u16 master_data; u8 speed = adev->dma_mode; int devid = adev->devno + 2 * ap->port_no; u8 udma_enable = 0; - static const /* ISP RTC */ - u8 timings[][2] = { { 0, 0 }, - { 0, 0 }, - { 1, 0 }, - { 2, 1 }, - { 2, 3 }, }; - - pci_read_config_word(dev, master_port, &master_data); - pci_read_config_byte(dev, 0x48, &udma_enable); - if (speed >= XFER_UDMA_0) { - unsigned int udma = adev->dma_mode - XFER_UDMA_0; + unsigned int udma = speed - XFER_UDMA_0; u16 udma_timing; u16 ideconf; int u_clock, u_speed; + pci_read_config_byte(dev, 0x48, &udma_enable); + /* * UDMA is handled by a combination of clock switching and * selection of dividers @@ -227,50 +226,18 @@ static void rdc_set_dmamode(struct ata_port *ap, struct ata_device *adev) ideconf &= ~(0x1001 << devid); ideconf |= u_clock << devid; pci_write_config_word(dev, 0x54, ideconf); + + pci_write_config_byte(dev, 0x48, udma_enable); } else { - /* - * MWDMA is driven by the PIO timings. We must also enable - * IORDY unconditionally along with TIME1. PPE has already - * been set when the PIO timing was set. - */ - unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; - unsigned int control; - u8 slave_data; + /* MWDMA is driven by the PIO timings. */ + unsigned int mwdma = speed - XFER_MW_DMA_0; const unsigned int needed_pio[3] = { XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 }; int pio = needed_pio[mwdma] - XFER_PIO_0; - control = 3; /* IORDY|TIME1 */ - - /* If the drive MWDMA is faster than it can do PIO then - we must force PIO into PIO0 */ - - if (adev->pio_mode < needed_pio[mwdma]) - /* Enable DMA timing only */ - control |= 8; /* PIO cycles in PIO0 */ - - if (adev->devno) { /* Slave */ - master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ - master_data |= control << 4; - pci_read_config_byte(dev, 0x44, &slave_data); - slave_data &= (ap->port_no ? 0x0f : 0xf0); - /* Load the matching timing */ - slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); - pci_write_config_byte(dev, 0x44, slave_data); - } else { /* Master */ - master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY - and master timing bits */ - master_data |= control; - master_data |= - (timings[pio][0] << 12) | - (timings[pio][1] << 8); - } - - udma_enable &= ~(1 << devid); - pci_write_config_word(dev, master_port, master_data); + rdc_set_timings(ap, adev, pio, 1); } - pci_write_config_byte(dev, 0x48, udma_enable); } static struct ata_port_operations rdc_pata_ops = {