From patchwork Sat Oct 7 02:28:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sukadev Bhattiprolu X-Patchwork-Id: 822900 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3y89w46wyyz9t3t for ; Sat, 7 Oct 2017 13:49:56 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3y89w464fXzDsjh for ; Sat, 7 Oct 2017 13:49:56 +1100 (AEDT) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from ozlabs.org (bilbo.ozlabs.org [103.22.144.67]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3y89Rr0Rc6zDqp6 for ; Sat, 7 Oct 2017 13:28:56 +1100 (AEDT) Received: from ozlabs.org (bilbo.ozlabs.org [103.22.144.67]) by bilbo.ozlabs.org (Postfix) with ESMTP id 3y89Rq6GWrz8vjD for ; Sat, 7 Oct 2017 13:28:55 +1100 (AEDT) Received: by ozlabs.org (Postfix) id 3y89Rq5fFgz9t7B; Sat, 7 Oct 2017 13:28:55 +1100 (AEDT) Delivered-To: linuxppc-dev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=sukadev@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3y89Rq2mzpz9t3C for ; Sat, 7 Oct 2017 13:28:55 +1100 (AEDT) Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v972QQFQ074668 for ; Fri, 6 Oct 2017 22:28:53 -0400 Received: from e34.co.us.ibm.com (e34.co.us.ibm.com [32.97.110.152]) by mx0a-001b2d01.pphosted.com with ESMTP id 2demj8b0hr-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Fri, 06 Oct 2017 22:28:53 -0400 Received: from localhost by e34.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 6 Oct 2017 20:28:49 -0600 Received: from b03ledav004.gho.boulder.ibm.com (b03ledav004.gho.boulder.ibm.com [9.17.130.235]) by b03cxnp07029.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v972Snej9830848; Fri, 6 Oct 2017 19:28:49 -0700 Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 284E97803F; Fri, 6 Oct 2017 20:28:49 -0600 (MDT) Received: from suka-w540.usor.ibm.com (unknown [9.70.94.25]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTP id 9306078041; Fri, 6 Oct 2017 20:28:48 -0600 (MDT) From: Sukadev Bhattiprolu To: Michael Ellerman Subject: [PATCH v2 15/18] powerpc: Emulate paste instruction Date: Fri, 6 Oct 2017 19:28:15 -0700 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507343298-27496-1-git-send-email-sukadev@linux.vnet.ibm.com> References: <1507343298-27496-1-git-send-email-sukadev@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 17100702-0016-0000-0000-0000079F122C X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00007853; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000235; SDB=6.00927531; UDB=6.00466725; IPR=6.00707787; BA=6.00005623; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00017430; XFM=3.00000015; UTC=2017-10-07 02:28:51 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17100702-0017-0000-0000-00003BC1C32E Message-Id: <1507343298-27496-16-git-send-email-sukadev@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-10-07_01:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1710070033 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mikey@neuling.org, linux-kernel@vger.kernel.org, nicholas.piggin@gmail.com, linuxppc-dev@ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Michael Neuling On POWER9 DD2.1 and below there are issues when the paste instruction generates an error. If an error occurs when thread reconfiguration happens (ie another thread in the core goes into/out of powersave) the core may hang. To avoid this a special sequence is required which stops thread configuration so that the paste can be safely executed. This patch assumes paste executed in userspace are trapped into the illegal instruction exception at 0xe40. Here we re-execute the paste instruction but with the required sequence to ensure thread reconfiguration doesn't occur. Signed-off-by: Michael Neuling Signed-off-by: Sukadev Bhattiprolu --- Edit by Sukadev: Use PPC_PASTE() rather than the paste instruction since in older versions the instruction required a third parameter. --- arch/powerpc/include/asm/emulated_ops.h | 1 + arch/powerpc/include/asm/ppc-opcode.h | 1 + arch/powerpc/include/asm/reg.h | 2 ++ arch/powerpc/kernel/traps.c | 64 +++++++++++++++++++++++++++++++++ 4 files changed, 68 insertions(+) diff --git a/arch/powerpc/include/asm/emulated_ops.h b/arch/powerpc/include/asm/emulated_ops.h index f00e10e..9247af9 100644 --- a/arch/powerpc/include/asm/emulated_ops.h +++ b/arch/powerpc/include/asm/emulated_ops.h @@ -55,6 +55,7 @@ extern struct ppc_emulated { struct ppc_emulated_entry mfdscr; struct ppc_emulated_entry mtdscr; struct ppc_emulated_entry lq_stq; + struct ppc_emulated_entry paste; #endif } ppc_emulated; diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index ce0930d..a55d2ef 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -229,6 +229,7 @@ #define PPC_INST_MTTMR 0x7c0003dc #define PPC_INST_NOP 0x60000000 #define PPC_INST_PASTE 0x7c20070d +#define PPC_INST_PASTE_MASK 0xfc2007ff #define PPC_INST_POPCNTB 0x7c0000f4 #define PPC_INST_POPCNTB_MASK 0xfc0007fe #define PPC_INST_POPCNTD 0x7c0003f4 diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index f92eaf7..5cde1c4 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -468,6 +468,8 @@ #define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */ #define SPRN_PPR 0x380 /* SMT Thread status Register */ #define SPRN_TSCR 0x399 /* Thread Switch Control Register */ +#define SPRN_TRIG1 0x371 /* WAT Trigger 1 */ +#define SPRN_TRIG2 0x372 /* WAT Trigger 2 */ #define SPRN_DEC 0x016 /* Decrement Register */ #define SPRN_DER 0x095 /* Debug Enable Register */ diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c index 13c9dcd..7e6b1fe 100644 --- a/arch/powerpc/kernel/traps.c +++ b/arch/powerpc/kernel/traps.c @@ -956,6 +956,65 @@ static inline bool tm_abort_check(struct pt_regs *regs, int reason) } #endif +static DEFINE_SPINLOCK(paste_emulation_lock); + +static inline int paste(void *i) +{ + int cr; + long retval = 0; + + /* Need per core lock to ensure trig1/2 writes don't race */ + spin_lock(&paste_emulation_lock); + mtspr(SPRN_TRIG1, 0); /* data doesn't matter */ + mtspr(SPRN_TRIG1, 0); /* HW says do this twice */ + asm volatile( + "1: " PPC_PASTE(0, %2) "\n" + "2: mfcr %1\n" + ".section .fixup,\"ax\"\n" + "3: li %0,%3\n" + " li %2,0\n" + " b 2b\n" + ".previous\n" + EX_TABLE(1b, 3b) + : "=r" (retval), "=r" (cr) + : "b" (i), "i" (-EFAULT), "0" (retval)); + mtspr(SPRN_TRIG2, 0); + spin_unlock(&paste_emulation_lock); + return cr; +} + +static int emulate_paste(struct pt_regs *regs, u32 instword) +{ + const void __user *addr; + unsigned long ea; + u8 ra, rb; + + if (!cpu_has_feature(CPU_FTR_ARCH_300)) + return -EINVAL; + + ra = (instword >> 16) & 0x1f; + rb = (instword >> 11) & 0x1f; + + ea = regs->gpr[rb] + (ra ? regs->gpr[ra] : 0ul); + if (is_32bit_task()) + ea &= 0xfffffffful; + addr = (__force const void __user *)ea; + + if (!access_ok(VERIFY_WRITE, addr, 128)) // cacheline size == 128 + return -EFAULT; + + hard_irq_disable(); /* FIXME: could we just soft disable ?? */ + pagefault_disable(); + + PPC_WARN_EMULATED(paste, regs); + regs->ccr = paste((void *)addr); + + pagefault_enable(); + may_hard_irq_enable(); + + return 0; +} + static int emulate_instruction(struct pt_regs *regs) { u32 instword; @@ -968,6 +1027,10 @@ static int emulate_instruction(struct pt_regs *regs) if (get_user(instword, (u32 __user *)(regs->nip))) return -EFAULT; + /* Emulate the paste RA, RB. */ + if ((instword & PPC_INST_PASTE_MASK) == PPC_INST_PASTE) + return emulate_paste(regs, instword); + /* Emulate the mfspr rD, PVR. */ if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { PPC_WARN_EMULATED(mfpvr, regs); @@ -1924,6 +1987,7 @@ struct ppc_emulated ppc_emulated = { WARN_EMULATED_SETUP(mfdscr), WARN_EMULATED_SETUP(mtdscr), WARN_EMULATED_SETUP(lq_stq), + WARN_EMULATED_SETUP(paste), #endif };