From patchwork Tue Oct 3 23:02:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 821062 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="EXbQ3494"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y6F392v27z9sNr for ; Wed, 4 Oct 2017 10:04:21 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751749AbdJCXEU (ORCPT ); Tue, 3 Oct 2017 19:04:20 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:49902 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751148AbdJCXDX (ORCPT ); Tue, 3 Oct 2017 19:03:23 -0400 Received: by mail-wm0-f66.google.com with SMTP id b189so15607206wmd.4; Tue, 03 Oct 2017 16:03:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=GxoPK/YmzpmSI2986xATxxHdP4mnOCJ8Cbj0lPN++6A=; b=EXbQ3494uE0QBezRNYTDb1iBwmUNWDuGDwImYdN92k3mUhG/F9KWwJ8SXB2kd/91Dz XBHJljLSeHpKkkK66TLK6frpM2LQVAo6X4q82RR+pP316oRuWluLgvBn8pC+zW6igLHi r6sZkn/Xwy3+UBjizlCz8g6swOFQaaUDP+Hy4knhTUEsZszbsoXUxr3eYus406K141Hm iNkTNTfxm/zjSaKUgwbG91tWC9EMQYWFMmrquzEWNF1+PNJLY4kNdMLhB65BxY4Ci0rJ 1nIrs+LKXu0G9rmfRw6Nkg8cNHdKLf2AZVZ+rICrGc537xbqgrGyiOPQawzuY9ImOzHH XLag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=GxoPK/YmzpmSI2986xATxxHdP4mnOCJ8Cbj0lPN++6A=; b=C7dN9BQBUfxid6DkkDANi8X2jKSJV7vfEqsTR7op078nvs3ts6FtFS2v0GMLSeHsK2 vcAHNx1MXCmWB3PyhtUjCydppADoT/phy1RGg4yz1aE87Ny0HoXgmJco75udUZ7uajgs E78HVSPD6UOL9v6ww7MRekKsudkqLcCrKvluwJzErWIKFDGRsNsyhU/xwS83CD5aCY/+ CEMkLkNo9XcVnMJoogmNro7lshn54hjVbQMggY58acri5P02BRVXZwLKIaf3OJh2oTT+ e00fO3witdmFPg6U2FB8wCIiVVP2HOP2H09jNxqGM0cdj2Jw73gzMEfrfBZMmuWC9Pz0 hEKQ== X-Gm-Message-State: AMCzsaUuZMu9NBtJR364qHU5kxDM6ARma0LLkvNtNcowxPxIT/Mrku2q PYr9MmokYvqA0dZIIVMIUAQ= X-Google-Smtp-Source: AOwi7QAZeVP9o53LfOZZcMBsnFLkosyz/6GtxFrow8dT0qKpysKjvpRRL6ftFOolOlZrmXnLwwV9+g== X-Received: by 10.28.213.75 with SMTP id m72mr7848760wmg.17.1507071801718; Tue, 03 Oct 2017 16:03:21 -0700 (PDT) Received: from localhost.localdomain (ppp109-252-55-163.pppoe.spdop.ru. [109.252.55.163]) by smtp.gmail.com with ESMTPSA id w82sm17971587wme.5.2017.10.03.16.03.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 03 Oct 2017 16:03:21 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/4] clk: tegra: Add AHB DMA clock entry Date: Wed, 4 Oct 2017 02:02:38 +0300 Message-Id: X-Mailer: git-send-email 2.14.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org AHB DMA engine presents on Tegra20/30. Add missing clock entries, so that driver for the AHB DMA controller could be implemented. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-id.h | 1 + drivers/clk/tegra/clk-tegra-periph.c | 1 + drivers/clk/tegra/clk-tegra20.c | 1 + drivers/clk/tegra/clk-tegra30.c | 1 + 4 files changed, 4 insertions(+) diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h index 689f344377a7..c1661b47bbda 100644 --- a/drivers/clk/tegra/clk-id.h +++ b/drivers/clk/tegra/clk-id.h @@ -12,6 +12,7 @@ enum clk_id { tegra_clk_amx, tegra_clk_amx1, tegra_clk_apb2ape, + tegra_clk_ahbdma, tegra_clk_apbdma, tegra_clk_apbif, tegra_clk_ape, diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c index 848255cc0209..0bce2bc55f0d 100644 --- a/drivers/clk/tegra/clk-tegra-periph.c +++ b/drivers/clk/tegra/clk-tegra-periph.c @@ -823,6 +823,7 @@ static struct tegra_periph_init_data gate_clks[] = { GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL), GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0), GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0), + GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0), GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0), GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0), GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0), diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 837e5cbd60e9..42740aad8791 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -522,6 +522,7 @@ static struct tegra_devclk devclks[] __initdata = { }; static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = { + [tegra_clk_ahbdma] = { .dt_id = TEGRA20_CLK_AHBDMA, .present = true }, [tegra_clk_spdif_out] = { .dt_id = TEGRA20_CLK_SPDIF_OUT, .present = true }, [tegra_clk_spdif_in] = { .dt_id = TEGRA20_CLK_SPDIF_IN, .present = true }, [tegra_clk_sdmmc1] = { .dt_id = TEGRA20_CLK_SDMMC1, .present = true }, diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index a2d163f759b4..ee168b0d9023 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -788,6 +788,7 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = { [tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true }, [tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true }, [tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true }, + [tegra_clk_ahbdma] = { .dt_id = TEGRA30_CLK_AHBDMA, .present = true }, [tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true }, [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true }, [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },