Patchwork [U-Boot] powerpc/qoriq: Use BR_PHYS_ADDR macro to setup BRs on P1_P2_RDB

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Submitter poonam aggrwal
Date Feb. 7, 2011, 9:38 a.m.
Message ID <1297071509-8595-1-git-send-email-poonam.aggrwal@freescale.com>
Download mbox | patch
Permalink /patch/82087/
State Accepted
Commit 09f9ee1695136045f293dacda915d94c2891d4f0
Delegated to: Kumar Gala
Headers show

Comments

poonam aggrwal - Feb. 7, 2011, 9:38 a.m.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
---
Based of: git://git.am.freescale.net/mirrors/u-boot.git (branch, master)
 include/configs/P1_P2_RDB.h |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)
Kumar Gala - Feb. 10, 2011, 5:32 a.m.
On Feb 7, 2011, at 3:38 AM, Poonam Aggrwal wrote:

> 
> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
> ---
> Based of: git://git.am.freescale.net/mirrors/u-boot.git (branch, master)
> include/configs/P1_P2_RDB.h |    5 +++--
> 1 files changed, 3 insertions(+), 2 deletions(-)

applied to 85xx next

- k

Patch

diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index 579abc2..607ebb8 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -267,7 +267,7 @@  extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 
 /* NAND flash config */
-#define CONFIG_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE_PHYS \
+#define CONFIG_NAND_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
 				| BR_PS_8	/* Port Size = 8 bit */ \
 				| BR_MS_FCM		/* MSEL = FCM */ \
@@ -297,7 +297,8 @@  extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_SYS_VSC7385_BASE_PHYS	CONFIG_SYS_VSC7385_BASE
 
-#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
+#define CONFIG_SYS_BR2_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE) \
+							| BR_PS_8 | BR_V)
 #define CONFIG_SYS_OR2_PRELIM	(OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 				OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
 				OR_GPCM_EHTR | OR_GPCM_EAD)