[RFC,1/2] phb4: Use read/write primitives when accessing PHB registers

Message ID 20171002222301.22832-2-gpiccoli@linux.vnet.ibm.com
State New
Headers show
Series
  • Some changes in phb4
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Commit Message

Guilherme G. Piccoli Oct. 2, 2017, 10:23 p.m.
Currently, the PHB registers access is mix-performed by the read/write
primitives or the open coded in/out procedures.

This patch change all open coded in/outs to use the read/write primitives.
No functional change is expected.

Signed-off-by: Guilherme G. Piccoli <gpiccoli@linux.vnet.ibm.com>
---
 hw/phb4.c | 418 +++++++++++++++++++++++++++++++-------------------------------
 1 file changed, 209 insertions(+), 209 deletions(-)

Comments

Michael Neuling Oct. 3, 2017, 12:40 a.m. | #1
On Mon, 2017-10-02 at 19:23 -0300, Guilherme G. Piccoli wrote:
> Currently, the PHB registers access is mix-performed by the read/write
> primitives or the open coded in/out procedures.
> 
> This patch change all open coded in/outs to use the read/write primitives.
> No functional change is expected.
> 
> Signed-off-by: Guilherme G. Piccoli <gpiccoli@linux.vnet.ibm.com>

I've been wanting to do this cleanup.  I've not tested but looks good to me.

Acked-by: Michael Neuling <mikey@neuling.org>

> ---
>  hw/phb4.c | 418 +++++++++++++++++++++++++++++++----------------------------
> ---
>  1 file changed, 209 insertions(+), 209 deletions(-)
> 
> diff --git a/hw/phb4.c b/hw/phb4.c
> index b94d4925..99902d3a 100644
> --- a/hw/phb4.c
> +++ b/hw/phb4.c
> @@ -480,7 +480,7 @@ static int64_t phb4_pcicfg_read(struct phb4 *p, uint32_t
> bdfn,
>  			return OPAL_PARAMETER;
>  		}
>  	} else {
> -		out_be64(p->regs + PHB_CONFIG_ADDRESS, addr);
> +		phb4_write_reg(p, PHB_CONFIG_ADDRESS, addr);
>  		switch(size) {
>  		case 1:
>  			*((uint8_t *)data) =
> @@ -559,7 +559,7 @@ static int64_t phb4_pcicfg_write(struct phb4 *p, uint32_t
> bdfn,
>  		/* We don't support ASB config space writes */
>  		return OPAL_UNSUPPORTED;
>  	} else {
> -		out_be64(p->regs + PHB_CONFIG_ADDRESS, addr);
> +		phb4_write_reg(p, PHB_CONFIG_ADDRESS, addr);
>  		switch(size) {
>  		case 1:
>  			out_8(p->regs + PHB_CONFIG_DATA + (offset & 3),
> data);
> @@ -977,7 +977,7 @@ static int64_t phb4_wait_bit(struct phb4 *p, uint32_t reg,
>  		return OPAL_SUCCESS;
>  
>  	for (;;) {
> -		val = in_be64(p->regs + reg);
> +		val = phb4_read_reg(p, reg);
>  		if (val == 0xffffffffffffffffull) {
>  			/* XXX Fenced ? */
>  			return OPAL_HARDWARE;
> @@ -1035,7 +1035,7 @@ static int64_t phb4_tce_kill(struct phb *phb, uint32_t
> kill_type,
>  				return OPAL_PARAMETER;
>  			}
>  			/* Perform kill */
> -			out_be64(p->regs + PHB_TCE_KILL, PHB_TCE_KILL_ONE |
> val);
> +			phb4_write_reg(p, PHB_TCE_KILL, PHB_TCE_KILL_ONE |
> val);
>  			/* Next page */
>  			dma_addr += tce_size;
>  		}
> @@ -1049,7 +1049,7 @@ static int64_t phb4_tce_kill(struct phb *phb, uint32_t
> kill_type,
>  		if (rc)
>  			return rc;
>  		/* Perform kill */
> -		out_be64(p->regs + PHB_TCE_KILL, PHB_TCE_KILL_PE |
> +		phb4_write_reg(p, PHB_TCE_KILL, PHB_TCE_KILL_PE |
>  			 SETFIELD(PHB_TCE_KILL_PENUM, 0ull, pe_number));
>  		break;
>  	case OPAL_PCI_TCE_KILL_ALL:
> @@ -1061,14 +1061,14 @@ static int64_t phb4_tce_kill(struct phb *phb, uint32_t
> kill_type,
>  		if (rc)
>  			return rc;
>  		/* Perform kill */
> -		out_be64(p->regs + PHB_TCE_KILL, PHB_TCE_KILL_ALL);
> +		phb4_write_reg(p, PHB_TCE_KILL, PHB_TCE_KILL_ALL);
>  		break;
>  	default:
>  		return OPAL_PARAMETER;
>  	}
>  
>  	/* Start DMA sync process */
> -	out_be64(p->regs + PHB_DMARD_SYNC, PHB_DMARD_SYNC_START);
> +	phb4_write_reg(p, PHB_DMARD_SYNC, PHB_DMARD_SYNC_START);
>  
>  	/* Wait for kill to complete */
>  	rc = phb4_wait_bit(p, PHB_Q_DMA_R, PHB_Q_DMA_R_TCE_KILL_STATUS, 0);
> @@ -1104,37 +1104,37 @@ static int64_t phb4_ioda_reset(struct phb *phb, bool
> purge)
>  
>  	/* Init_30..31 - Errata workaround, clear PESTA entry 0 */
>  	phb4_ioda_sel(p, IODA3_TBL_PESTA, 0, false);
> -	out_be64(p->regs + PHB_IODA_DATA0, 0);
> +	phb4_write_reg(p, PHB_IODA_DATA0, 0);
>  
>  	/* Init_32..33 - MIST  */
>  	phb4_ioda_sel(p, IODA3_TBL_MIST, 0, true);
> -	val = in_be64(p->regs + PHB_IODA_ADDR);
> +	val = phb4_read_reg(p, PHB_IODA_ADDR);
>  	val = SETFIELD(PHB_IODA_AD_MIST_PWV, val, 0xf);
> -	out_be64(p->regs + PHB_IODA_ADDR, val);
> +	phb4_write_reg(p, PHB_IODA_ADDR, val);
>  	for (i = 0; i < (p->num_irqs/4); i++)
> -		out_be64(p->regs + PHB_IODA_DATA0, p->mist_cache[i]);
> +		phb4_write_reg(p, PHB_IODA_DATA0, p->mist_cache[i]);
>  
>  	/* Init_34..35 - MRT */
>  	phb4_ioda_sel(p, IODA3_TBL_MRT, 0, true);
>  	for (i = 0; i < p->mrt_size; i++)
> -		out_be64(p->regs + PHB_IODA_DATA0, 0);
> +		phb4_write_reg(p, PHB_IODA_DATA0, 0);
>  
>  	/* Init_36..37 - TVT */
>  	phb4_ioda_sel(p, IODA3_TBL_TVT, 0, true);
>  	for (i = 0; i < p->tvt_size; i++)
> -		out_be64(p->regs + PHB_IODA_DATA0, p->tve_cache[i]);
> +		phb4_write_reg(p, PHB_IODA_DATA0, p->tve_cache[i]);
>  
>  	/* Init_38..39 - MBT */
>  	phb4_ioda_sel(p, IODA3_TBL_MBT, 0, true);
>  	for (i = 0; i < p->mbt_size; i++) {
> -		out_be64(p->regs + PHB_IODA_DATA0, p->mbt_cache[i][0]);
> -		out_be64(p->regs + PHB_IODA_DATA0, p->mbt_cache[i][1]);
> +		phb4_write_reg(p, PHB_IODA_DATA0, p->mbt_cache[i][0]);
> +		phb4_write_reg(p, PHB_IODA_DATA0, p->mbt_cache[i][1]);
>  	}
>  
>  	/* Init_40..41 - MDT */
>  	phb4_ioda_sel(p, IODA3_TBL_MDT, 0, true);
>  	for (i = 0; i < p->max_num_pes; i++)
> -		out_be64(p->regs + PHB_IODA_DATA0, p->mdt_cache[i]);
> +		phb4_write_reg(p, PHB_IODA_DATA0, p->mdt_cache[i]);
>  
>  	/* Additional OPAL specific inits */
>  
> @@ -1147,17 +1147,17 @@ static int64_t phb4_ioda_reset(struct phb *phb, bool
> purge)
>  	/* Clear PEST & PEEV */
>  	for (i = 0; i < p->max_num_pes; i++) {
>  		phb4_ioda_sel(p, IODA3_TBL_PESTA, i, false);
> -		out_be64(p->regs + PHB_IODA_DATA0, 0);
> +		phb4_write_reg(p, PHB_IODA_DATA0, 0);
>  		phb4_ioda_sel(p, IODA3_TBL_PESTB, i, false);
> -		out_be64(p->regs + PHB_IODA_DATA0, 0);
> +		phb4_write_reg(p, PHB_IODA_DATA0, 0);
>  	}
>  
>  	phb4_ioda_sel(p, IODA3_TBL_PEEV, 0, true);
>  	for (i = 0; i < p->max_num_pes/64; i++)
> -		out_be64(p->regs + PHB_IODA_DATA0, 0);
> +		phb4_write_reg(p, PHB_IODA_DATA0, 0);
>  
>  	/* Invalidate RTE, TCE cache */
> -	out_be64(p->regs + PHB_RTC_INVALIDATE, PHB_RTC_INVALIDATE_ALL);
> +	phb4_write_reg(p, PHB_RTC_INVALIDATE, PHB_RTC_INVALIDATE_ALL);
>  
>  	return phb4_tce_kill(&p->phb, OPAL_PCI_TCE_KILL_ALL, 0, 0, 0, 0);
>  }
> @@ -1173,9 +1173,9 @@ static int64_t phb4_papr_errinjct_reset(struct phb *phb)
>  {
>  	struct phb4 *p = phb_to_phb4(phb);
>  
> -	out_be64(p->regs + PHB_PAPR_ERR_INJ_CTL, 0x0ul);
> -	out_be64(p->regs + PHB_PAPR_ERR_INJ_ADDR, 0x0ul);
> -	out_be64(p->regs + PHB_PAPR_ERR_INJ_MASK, 0x0ul);
> +	phb4_write_reg(p, PHB_PAPR_ERR_INJ_CTL, 0x0ul);
> +	phb4_write_reg(p, PHB_PAPR_ERR_INJ_ADDR, 0x0ul);
> +	phb4_write_reg(p, PHB_PAPR_ERR_INJ_MASK, 0x0ul);
>  
>  	return OPAL_SUCCESS;
>  }
> @@ -1353,8 +1353,8 @@ static int64_t phb4_phb_mmio_enable(struct phb __unused
> *phb,
>  	p->mbt_cache[window_num][0] = mbt0;
>  	p->mbt_cache[window_num][1] = mbt1;
>  	phb4_ioda_sel(p, IODA3_TBL_MBT, window_num << 1, true);
> -	out_be64(p->regs + PHB_IODA_DATA0, mbt0);
> -	out_be64(p->regs + PHB_IODA_DATA0, mbt1);
> +	phb4_write_reg(p, PHB_IODA_DATA0, mbt0);
> +	phb4_write_reg(p, PHB_IODA_DATA0, mbt1);
>  
>  	return OPAL_SUCCESS;
>  }
> @@ -1404,13 +1404,13 @@ static int64_t phb4_map_pe_mmio_window(struct phb
> *phb,
>  			p->mdt_cache[segment_num << 1] = mdt0;
>  			p->mdt_cache[(segment_num << 1) + 1] = mdt1;
>  			phb4_ioda_sel(p, IODA3_TBL_MDT, segment_num << 1,
> true);
> -			out_be64(p->regs + PHB_IODA_DATA0, mdt0);
> -			out_be64(p->regs + PHB_IODA_DATA0, mdt1);
> +			phb4_write_reg(p, PHB_IODA_DATA0, mdt0);
> +			phb4_write_reg(p, PHB_IODA_DATA0, mdt1);
>  		} else {
>  			mdt0 = p->mdt_cache[segment_num];
>  			mdt0 = SETFIELD(IODA3_MDT_PE_A, mdt0, pe_number);
>  			phb4_ioda_sel(p, IODA3_TBL_MDT, segment_num, false);
> -			out_be64(p->regs + PHB_IODA_DATA0, mdt0);
> +			phb4_write_reg(p, PHB_IODA_DATA0, mdt0);
>  		}
>  		break;
>  	case OPAL_M64_WINDOW_TYPE:
> @@ -1471,7 +1471,7 @@ static int64_t phb4_map_pe_dma_window(struct phb *phb,
>  	 */
>  	if (tce_table_size == 0) {
>  		phb4_ioda_sel(p, IODA3_TBL_TVT, window_id, false);
> -		out_be64(p->regs + PHB_IODA_DATA0, 0);
> +		phb4_write_reg(p, PHB_IODA_DATA0, 0);
>  		p->tve_cache[window_id] = 0;
>  		return OPAL_SUCCESS;
>  	}
> @@ -1511,7 +1511,7 @@ static int64_t phb4_map_pe_dma_window(struct phb *phb,
>  	data64 = SETFIELD(IODA3_TVT_NUM_LEVELS, data64, tce_levels - 1);
>  
>  	phb4_ioda_sel(p, IODA3_TBL_TVT, window_id, false);
> -	out_be64(p->regs + PHB_IODA_DATA0, data64);
> +	phb4_write_reg(p, PHB_IODA_DATA0, data64);
>  	p->tve_cache[window_id] = data64;
>  
>  	return OPAL_SUCCESS;
> @@ -1574,7 +1574,7 @@ static int64_t phb4_map_pe_dma_window_real(struct phb
> *phb,
>  	}
>  
>  	phb4_ioda_sel(p, IODA3_TBL_TVT, window_id, false);
> -	out_be64(p->regs + PHB_IODA_DATA0, tve);
> +	phb4_write_reg(p, PHB_IODA_DATA0, tve);
>  	p->tve_cache[window_id] = tve;
>  
>  	return OPAL_SUCCESS;
> @@ -1608,12 +1608,12 @@ static int64_t phb4_set_ive_pe(struct phb *phb,
>  	/* We need to inject the appropriate MIST write enable bit
>  	 * in the IODA table address register
>  	 */
> -	val = in_be64(p->regs + PHB_IODA_ADDR);
> +	val = phb4_read_reg(p, PHB_IODA_ADDR);
>  	val = SETFIELD(PHB_IODA_AD_MIST_PWV, val, 8 >> mist_quad);
> -	out_be64(p->regs + PHB_IODA_ADDR, val);
> +	phb4_write_reg(p, PHB_IODA_ADDR, val);
>  
>  	/* Write entry */
> -	out_be64(p->regs + PHB_IODA_DATA0, p->mist_cache[mist_idx]);
> +	phb4_write_reg(p, PHB_IODA_DATA0, p->mist_cache[mist_idx]);
>  
>  	return OPAL_SUCCESS;
>  }
> @@ -2074,7 +2074,7 @@ static int64_t phb4_set_pe(struct phb *phb,
>  	}
>  
>  	/* Invalidate the entire RTC */
> -	out_be64(p->regs + PHB_RTC_INVALIDATE, PHB_RTC_INVALIDATE_ALL);
> +	phb4_write_reg(p, PHB_RTC_INVALIDATE, PHB_RTC_INVALIDATE_ALL);
>  
>  	return OPAL_SUCCESS;
>  }
> @@ -2135,15 +2135,15 @@ static void phb4_prepare_link_change(struct pci_slot
> *slot, bool is_up)
>  		p->flags &= ~PHB4_CFG_BLOCKED;
>  
>  		/* Re-enable link down errors */
> -		out_be64(p->regs + PHB_PCIE_MISC_STRAP,
> +		phb4_write_reg(p, PHB_PCIE_MISC_STRAP,
>  			 0x0000060000000000ull);
>  
>  		/* Re-enable error status indicators that trigger irqs */
> -		out_be64(p->regs + PHB_REGB_ERR_INF_ENABLE,
> +		phb4_write_reg(p, PHB_REGB_ERR_INF_ENABLE,
>  			 0x2130006efca8bc00ull);
> -		out_be64(p->regs + PHB_REGB_ERR_ERC_ENABLE,
> +		phb4_write_reg(p, PHB_REGB_ERR_ERC_ENABLE,
>  			 0x0000000000000000ull);
> -		out_be64(p->regs + PHB_REGB_ERR_FAT_ENABLE,
> +		phb4_write_reg(p, PHB_REGB_ERR_FAT_ENABLE,
>  			 0xde8fff91035743ffull);
>  
>  		/*
> @@ -2167,12 +2167,12 @@ static void phb4_prepare_link_change(struct pci_slot
> *slot, bool is_up)
>  				    PCIECAP_AER_CE_MASK, reg32);
>  
>  		/* Clear error link enable & error link down kill enable */
> -		out_be64(p->regs + PHB_PCIE_MISC_STRAP, 0);
> +		phb4_write_reg(p, PHB_PCIE_MISC_STRAP, 0);
>  
>  		/* Disable all error status indicators that trigger irqs */
> -		out_be64(p->regs + PHB_REGB_ERR_INF_ENABLE, 0);
> -		out_be64(p->regs + PHB_REGB_ERR_ERC_ENABLE, 0);
> -		out_be64(p->regs + PHB_REGB_ERR_FAT_ENABLE, 0);
> +		phb4_write_reg(p, PHB_REGB_ERR_INF_ENABLE, 0);
> +		phb4_write_reg(p, PHB_REGB_ERR_ERC_ENABLE, 0);
> +		phb4_write_reg(p, PHB_REGB_ERR_FAT_ENABLE, 0);
>  
>  		/* Block PCI-CFG access */
>  		p->flags |= PHB4_CFG_BLOCKED;
> @@ -2189,7 +2189,7 @@ static int64_t phb4_get_presence_state(struct pci_slot
> *slot, uint8_t *val)
>  		return OPAL_HARDWARE;
>  
>  	/* Check hotplug status */
> -	hps = in_be64(p->regs + PHB_PCIE_HOTPLUG_STATUS);
> +	hps = phb4_read_reg(p, PHB_PCIE_HOTPLUG_STATUS);
>  	if (!(hps & PHB_PCIE_HPSTAT_PRESENCE)) {
>  		*val = OPAL_PCI_SLOT_PRESENT;
>  	} else {
> @@ -2198,7 +2198,7 @@ static int64_t phb4_get_presence_state(struct pci_slot
> *slot, uint8_t *val)
>  		 * we are on a broken simulation environment and still
>  		 * return a valid presence. Otherwise, not present.
>  		 */
> -		dtctl = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
> +		dtctl = phb4_read_reg(p, PHB_PCIE_DLP_TRAIN_CTL);
>  		if (dtctl & PHB_PCIE_DLP_TL_LINKACT) {
>  			PHBERR(p, "Presence detect 0 but link set !\n");
>  			*val = OPAL_PCI_SLOT_PRESENT;
> @@ -2220,7 +2220,7 @@ static int64_t phb4_get_link_info(struct pci_slot *slot,
> uint8_t *speed,
>  	uint8_t s;
>  
>  	/* Link is up, let's find the actual speed */
> -	reg = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
> +	reg = phb4_read_reg(p, PHB_PCIE_DLP_TRAIN_CTL);
>  	if (!(reg & PHB_PCIE_DLP_TL_LINKACT)) {
>  		*width = 0;
>  		if (speed)
> @@ -2350,7 +2350,7 @@ static bool phb4_fenced(struct phb4 *p)
>  	 * An all 1's from the PHB indicates a PHB freeze/fence. We
>  	 * don't really differenciate them at this point.
>  	 */
> -	if (in_be64(p->regs + PHB_CPU_LOADSTORE_STATUS)!=
> 0xfffffffffffffffful)
> +	if (phb4_read_reg(p, PHB_CPU_LOADSTORE_STATUS)!=
> 0xfffffffffffffffful)
>  		return false;
>  
>  	PHBERR(p, "PHB Freeze/Fence detected !\n");
> @@ -2529,7 +2529,7 @@ static void phb4_training_trace(struct phb4 *p)
>  
>  	while(1) {
>  		now = mftb();
> -		reg = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
> +		reg = phb4_read_reg(p, PHB_PCIE_DLP_TRAIN_CTL);
>  		if (reg != reglast)
>  			phb4_train_info(p, reg, now - start);
>  		reglast = reg;
> @@ -2573,7 +2573,7 @@ static int64_t phb4_poll_link(struct pci_slot *slot)
>  		 * because simics doesn't seem to implement the electrical
>  		 * link bit at all
>  		 */
> -		reg = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
> +		reg = phb4_read_reg(p, PHB_PCIE_DLP_TRAIN_CTL);
>  		if (!phb4_check_reg(p, reg)) {
>  			PHBERR(p, "PHB fence waiting for electrical link\n");
>  			return phb4_retry_state(slot);
> @@ -2596,7 +2596,7 @@ static int64_t phb4_poll_link(struct pci_slot *slot)
>  		/* Retry */
>  		return pci_slot_set_sm_timeout(slot, msecs_to_tb(10));
>  	case PHB4_SLOT_LINK_WAIT:
> -		reg = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
> +		reg = phb4_read_reg(p, PHB_PCIE_DLP_TRAIN_CTL);
>  		if (!phb4_check_reg(p, reg)) {
>  			PHBERR(p, "LINK: PHB fence waiting for link
> training\n");
>  			return phb4_retry_state(slot);
> @@ -2621,7 +2621,7 @@ static int64_t phb4_poll_link(struct pci_slot *slot)
>  			PHBERR(p, "LINK: PHB fenced waiting for stabilty\n");
>  			return phb4_retry_state(slot);
>  		}
> -		reg = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
> +		reg = phb4_read_reg(p, PHB_PCIE_DLP_TRAIN_CTL);
>  		if (!phb4_check_reg(p, reg)) {
>  			PHBERR(p, "LINK: PHB fence reading training
> control\n");
>  			return phb4_retry_state(slot);
> @@ -2736,9 +2736,9 @@ static int64_t phb4_freset(struct pci_slot *slot)
>  	case PHB4_SLOT_FRESET_START:
>  		if (!p->skip_perst) {
>  			PHBDBG(p, "FRESET: Assert\n");
> -			reg = in_be64(p->regs + PHB_PCIE_CRESET);
> +			reg = phb4_read_reg(p, PHB_PCIE_CRESET);
>  			reg &= ~PHB_PCIE_CRESET_PERST_N;
> -			out_be64(p->regs + PHB_PCIE_CRESET, reg);
> +			phb4_write_reg(p, PHB_PCIE_CRESET, reg);
>  			pci_slot_set_state(slot,
>  				PHB4_SLOT_FRESET_ASSERT_DELAY);
>  			/* 250ms assert time aligns with powernv */
> @@ -2756,15 +2756,15 @@ static int64_t phb4_freset(struct pci_slot *slot)
>  
>  		if (pci_tracing) {
>  			/* Enable tracing */
> -			reg = in_be64(p->regs + PHB_PCIE_DLP_TRWCTL);
> -			out_be64(p->regs + PHB_PCIE_DLP_TRWCTL,
> +			reg = phb4_read_reg(p, PHB_PCIE_DLP_TRWCTL);
> +			phb4_write_reg(p, PHB_PCIE_DLP_TRWCTL,
>  				 reg | PHB_PCIE_DLP_TRWCTL_EN);
>  		}
>  
>  		PHBDBG(p, "FRESET: Deassert\n");
> -		reg = in_be64(p->regs + PHB_PCIE_CRESET);
> +		reg = phb4_read_reg(p, PHB_PCIE_CRESET);
>  		reg |= PHB_PCIE_CRESET_PERST_N;
> -		out_be64(p->regs + PHB_PCIE_CRESET, reg);
> +		phb4_write_reg(p, PHB_PCIE_CRESET, reg);
>  		pci_slot_set_state(slot,
>  			PHB4_SLOT_FRESET_DEASSERT_DELAY);
>  
> @@ -3002,7 +3002,7 @@ static int64_t phb4_eeh_freeze_status(struct phb *phb,
> uint64_t pe_number,
>  
>  	/* Check the PEEV */
>  	phb4_ioda_sel(p, IODA3_TBL_PEEV, pe_number / 64, false);
> -	peev = in_be64(p->regs + PHB_IODA_DATA0);
> +	peev = phb4_read_reg(p, PHB_IODA_DATA0);
>  	if (!(peev & peev_bit))
>  		return OPAL_SUCCESS;
>  
> @@ -3013,9 +3013,9 @@ static int64_t phb4_eeh_freeze_status(struct phb *phb,
> uint64_t pe_number,
>  
>  	/* Read the PESTA & PESTB */
>  	phb4_ioda_sel(p, IODA3_TBL_PESTA, pe_number, false);
> -	pesta = in_be64(p->regs + PHB_IODA_DATA0);
> +	pesta = phb4_read_reg(p, PHB_IODA_DATA0);
>  	phb4_ioda_sel(p, IODA3_TBL_PESTB, pe_number, false);
> -	pestb = in_be64(p->regs + PHB_IODA_DATA0);
> +	pestb = phb4_read_reg(p, PHB_IODA_DATA0);
>  
>  	/* Convert them */
>  	if (pesta & IODA3_PESTA_MMIO_FROZEN)
> @@ -3045,7 +3045,7 @@ static int64_t phb4_eeh_freeze_clear(struct phb *phb,
> uint64_t pe_number,
>  	 * contain a freeze state from a previous error or simply set
>  	 * explicitely by the user
>  	 */
> -	err = in_be64(p->regs + PHB_ETU_ERR_SUMMARY);
> +	err = phb4_read_reg(p, PHB_ETU_ERR_SUMMARY);
>  	if (err == 0xffffffffffffffff) {
>  		if (phb4_fenced(p)) {
>  			PHBERR(p, "eeh_freeze_clear on fenced PHB\n");
> @@ -3061,18 +3061,18 @@ static int64_t phb4_eeh_freeze_clear(struct phb *phb,
> uint64_t pe_number,
>  	 */
>  	if (eeh_action_token & OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO) {
>  		phb4_ioda_sel(p, IODA3_TBL_PESTA, pe_number, false);
> -		out_be64(p->regs + PHB_IODA_DATA0, 0);
> +		phb4_write_reg(p, PHB_IODA_DATA0, 0);
>  	}
>  	if (eeh_action_token & OPAL_EEH_ACTION_CLEAR_FREEZE_DMA) {
>  		phb4_ioda_sel(p, IODA3_TBL_PESTB, pe_number, false);
> -		out_be64(p->regs + PHB_IODA_DATA0, 0);
> +		phb4_write_reg(p, PHB_IODA_DATA0, 0);
>  	}
>  
>  
>  	/* Update ER pending indication */
>  	phb4_ioda_sel(p, IODA3_TBL_PEEV, 0, true);
>  	for (i = 0; i < p->num_pes/64; i++) {
> -		peev = in_be64(p->regs + PHB_IODA_DATA0);
> +		peev = phb4_read_reg(p, PHB_IODA_DATA0);
>  		if (peev) {
>  			frozen_pe = true;
>  			break;
> @@ -3108,16 +3108,16 @@ static int64_t phb4_eeh_freeze_set(struct phb *phb,
> uint64_t pe_number,
>  
>  	if (eeh_action_token & OPAL_EEH_ACTION_SET_FREEZE_MMIO) {
>  		phb4_ioda_sel(p, IODA3_TBL_PESTA, pe_number, false);
> -		data = in_be64(p->regs + PHB_IODA_DATA0);
> +		data = phb4_read_reg(p, PHB_IODA_DATA0);
>  		data |= IODA3_PESTA_MMIO_FROZEN;
> -		out_be64(p->regs + PHB_IODA_DATA0, data);
> +		phb4_write_reg(p, PHB_IODA_DATA0, data);
>  	}
>  
>  	if (eeh_action_token & OPAL_EEH_ACTION_SET_FREEZE_DMA) {
>  		phb4_ioda_sel(p, IODA3_TBL_PESTB, pe_number, false);
> -		data = in_be64(p->regs + PHB_IODA_DATA0);
> +		data = phb4_read_reg(p, PHB_IODA_DATA0);
>  		data |= IODA3_PESTB_DMA_STOPPED;
> -		out_be64(p->regs + PHB_IODA_DATA0, data);
> +		phb4_write_reg(p, PHB_IODA_DATA0, data);
>  	}
>  
>  	return OPAL_SUCCESS;
> @@ -3165,7 +3165,7 @@ static int64_t phb4_eeh_next_error(struct phb *phb,
>  	if (!phb4_err_pending(p)) {
>  		phb4_ioda_sel(p, IODA3_TBL_PEEV, 0, true);
>  		for (i = 0; i < peev_size; i++) {
> -			peev = in_be64(p->regs + PHB_IODA_DATA0);
> +			peev = phb4_read_reg(p, PHB_IODA_DATA0);
>  			if (peev) {
>  				p->err.err_src	 = PHB4_ERR_SRC_PHB;
>  				p->err.err_class = PHB4_ERR_CLASS_ER;
> @@ -3211,7 +3211,7 @@ static int64_t phb4_eeh_next_error(struct phb *phb,
>  
>  			for (i = peev_size - 1; i >= 0; i--) {
>  				phb4_ioda_sel(p, IODA3_TBL_PEEV, i, false);
> -				peev = in_be64(p->regs + PHB_IODA_DATA0);
> +				peev = phb4_read_reg(p, PHB_IODA_DATA0);
>  				for (j = 0; j < 64; j++) {
>  					if (peev & PPC_BIT(j)) {
>  						*first_frozen_pe = i * 64 +
> j;
> @@ -3254,9 +3254,9 @@ static int64_t phb4_err_inject_finalize(struct phb4
> *phb, uint64_t addr,
>  	else
>  		ctrl |= PHB_PAPR_ERR_INJ_CTL_RD;
>  
> -	out_be64(phb->regs + PHB_PAPR_ERR_INJ_ADDR, addr);
> -	out_be64(phb->regs + PHB_PAPR_ERR_INJ_MASK, mask);
> -	out_be64(phb->regs + PHB_PAPR_ERR_INJ_CTL, ctrl);
> +	phb4_write_reg(phb, PHB_PAPR_ERR_INJ_ADDR,	addr);
> +	phb4_write_reg(phb, PHB_PAPR_ERR_INJ_MASK,	mask);
> +	phb4_write_reg(phb, PHB_PAPR_ERR_INJ_CTL,	ctrl);
>  
>  	return OPAL_SUCCESS;
>  }
> @@ -3376,7 +3376,7 @@ static int64_t phb4_err_inject(struct phb *phb, uint64_t
> pe_number,
>  		return OPAL_PARAMETER;
>  
>  	/* Clear leftover from last time */
> -	out_be64(p->regs + PHB_PAPR_ERR_INJ_CTL, 0x0ul);
> +	phb4_write_reg(p, PHB_PAPR_ERR_INJ_CTL, 0x0ul);
>  
>  	switch (func) {
>  	case OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR:
> @@ -3628,19 +3628,19 @@ static void phb4_init_capp_regs(struct phb4 *p)
>  static void phb4_init_capp_errors(struct phb4 *p)
>  {
>  	/* Init_77: TXE Error AIB Fence Enable Register */
> -	out_be64(p->regs + 0x0d30,	0xdff7ff0bf7ddfff0ull);
> +	phb4_write_reg(p, 0x0d30,	0xdff7ff0bf7ddfff0ull);
>  
>  	/* Init_86: RXE_ARB Error AIB Fence Enable Register */
> -	out_be64(p->regs + 0x0db0,	0xfbffd7bbfb7fbfefull);
> +	phb4_write_reg(p, 0x0db0,	0xfbffd7bbfb7fbfefull);
>  
>  	/* Init_95: RXE_MRG Error AIB Fence Enable Register */
> -	out_be64(p->regs + 0x0e30,	0xfffffeffff7fff57ull);
> +	phb4_write_reg(p, 0x0e30,	0xfffffeffff7fff57ull);
>  
>  	/* Init_104: RXE_TCE Error AIB Fence Enable Register */
> -	out_be64(p->regs + 0x0eb0,	0xffaeffafffffffffull);
> +	phb4_write_reg(p, 0x0eb0,	0xffaeffafffffffffull);
>  
>  	/* Init_113: PHB Error AIB Fence Enable Register */
> -	out_be64(p->regs + 0x0cb0,	0x35777073ff000000ull);
> +	phb4_write_reg(p, 0x0cb0,	0x35777073ff000000ull);
>  }
>  
>  /* Power Bus Common Queue Registers
> @@ -3731,12 +3731,12 @@ static int64_t enable_capi_mode(struct phb4 *p,
> uint64_t pe_number,
>  	 * Bit [0:7] XSL_DSNCTL[capiind]
>  	 * Init_25 - CAPI Compare/Mask
>  	 */
> -	out_be64(p->regs + PHB_CAPI_CMPM,
> +	phb4_write_reg(p, PHB_CAPI_CMPM,
>  		 0x0200FE0000000000Ull | PHB_CAPI_CMPM_ENABLE);
>  
>  	if (!(p->rev == PHB4_REV_NIMBUS_DD10)) {
>  		/* Init_24 - ASN Compare/Mask */
> -		out_be64(p->regs + PHB_PBL_ASN_CMPM,
> +		phb4_write_reg(p, PHB_PBL_ASN_CMPM,
>  			 0x0400FF0000000000Ull | PHB_PBL_ASN_ENABLE);
>  
>  		/* PBCQ Tunnel Bar Register
> @@ -3761,7 +3761,7 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t
> pe_number,
>  	}
>  
>  	/* non-translate/50-bit mode */
> -	out_be64(p->regs + PHB_NXLATE_PREFIX, 0x0000000000000000Ull);
> +	phb4_write_reg(p, PHB_NXLATE_PREFIX, 0x0000000000000000Ull);
>  
>  	/* set tve no translate mode allow mmio window */
>  	memset(p->tve_cache, 0x0, sizeof(p->tve_cache));
> @@ -3800,7 +3800,7 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t
> pe_number,
>  
>  	phb4_ioda_sel(p, IODA3_TBL_TVT, 0, true);
>  	for (i = 0; i < p->tvt_size; i++)
> -		out_be64(p->regs + PHB_IODA_DATA0, p->tve_cache[i]);
> +		phb4_write_reg(p, PHB_IODA_DATA0, p->tve_cache[i]);
>  
>  	/* set mbt bar to pass capi mmio window. First applied cleared
>  	 * values to HW
> @@ -3811,8 +3811,8 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t
> pe_number,
>  	}
>  	phb4_ioda_sel(p, IODA3_TBL_MBT, 0, true);
>  	for (i = 0; i < p->mbt_size; i++) {
> -		out_be64(p->regs + PHB_IODA_DATA0, p->mbt_cache[i][0]);
> -		out_be64(p->regs + PHB_IODA_DATA0, p->mbt_cache[i][1]);
> +		phb4_write_reg(p, PHB_IODA_DATA0, p->mbt_cache[i][0]);
> +		phb4_write_reg(p, PHB_IODA_DATA0, p->mbt_cache[i][1]);
>  	}
>  
>  	p->mbt_cache[0][0] = IODA3_MBT0_ENABLE |
> @@ -3835,8 +3835,8 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t
> pe_number,
>  
>  	phb4_ioda_sel(p, IODA3_TBL_MBT, 0, true);
>  	for (i = 0; i < p->mbt_size; i++) {
> -		out_be64(p->regs + PHB_IODA_DATA0, p->mbt_cache[i][0]);
> -		out_be64(p->regs + PHB_IODA_DATA0, p->mbt_cache[i][1]);
> +		phb4_write_reg(p, PHB_IODA_DATA0, p->mbt_cache[i][0]);
> +		phb4_write_reg(p, PHB_IODA_DATA0, p->mbt_cache[i][1]);
>  	}
>  
>  	phb4_init_capp_errors(p);
> @@ -3923,7 +3923,7 @@ static void phb4_p2p_set_initiator(struct phb4 *p,
> uint16_t pe_number)
>  	PHBDBG(p, "Setting TVE#1 for peer-to-peer for pe %d\n", pe_number);
>  	tve = PPC_BIT(51);
>  	phb4_ioda_sel(p, IODA3_TBL_TVT, window_id, false);
> -	out_be64(p->regs + PHB_IODA_DATA0, tve);
> +	phb4_write_reg(p, PHB_IODA_DATA0, tve);
>  	p->tve_cache[window_id] = tve;
>  }
>  
> @@ -4027,29 +4027,29 @@ static const struct phb_ops phb4_ops = {
>  static void phb4_init_ioda3(struct phb4 *p)
>  {
>  	/* Init_18 - Interrupt Notify Base Address */
> -	out_be64(p->regs + PHB_INT_NOTIFY_ADDR, p->irq_port);
> +	phb4_write_reg(p, PHB_INT_NOTIFY_ADDR, p->irq_port);
>  
>  	/* Init_19 - Interrupt Notify Base Index */
> -	out_be64(p->regs + PHB_INT_NOTIFY_INDEX,
> +	phb4_write_reg(p, PHB_INT_NOTIFY_INDEX,
>  		 xive_get_notify_base(p->base_msi));
>  
>  	/* Init_19x - Not in spec: Initialize source ID */
>  	PHBDBG(p, "Reset state SRC_ID: %016llx\n",
> -	       in_be64(p->regs + PHB_LSI_SOURCE_ID));
> -	out_be64(p->regs + PHB_LSI_SOURCE_ID,
> +	       phb4_read_reg(p, PHB_LSI_SOURCE_ID));
> +	phb4_write_reg(p, PHB_LSI_SOURCE_ID,
>  		 SETFIELD(PHB_LSI_SRC_ID, 0ull, (p->num_irqs - 1) >> 3));
>  
>  	/* Init_20 - RTT BAR */
> -	out_be64(p->regs + PHB_RTT_BAR, p->tbl_rtt | PHB_RTT_BAR_ENABLE);
> +	phb4_write_reg(p, PHB_RTT_BAR, p->tbl_rtt | PHB_RTT_BAR_ENABLE);
>  
>  	/* Init_21 - PELT-V BAR */
> -	out_be64(p->regs + PHB_PELTV_BAR, p->tbl_peltv |
> PHB_PELTV_BAR_ENABLE);
> +	phb4_write_reg(p, PHB_PELTV_BAR, p->tbl_peltv |
> PHB_PELTV_BAR_ENABLE);
>  
>  	/* Init_22 - Setup M32 starting address */
> -	out_be64(p->regs + PHB_M32_START_ADDR, M32_PCI_START);
> +	phb4_write_reg(p, PHB_M32_START_ADDR, M32_PCI_START);
>  
>  	/* Init_23 - Setup PEST BAR */
> -	out_be64(p->regs + PHB_PEST_BAR,
> +	phb4_write_reg(p, PHB_PEST_BAR,
>  		 p->tbl_pest | PHB_PEST_BAR_ENABLE);
>  
>  	/* Init_24 - CRW Base Address Reg */
> @@ -4062,17 +4062,17 @@ static void phb4_init_ioda3(struct phb4 *p)
>  	/* See enable_capi_mode() */
>  
>  	/* Init_27 - PCIE Outbound upper address */
> -	out_be64(p->regs + PHB_M64_UPPER_BITS, 0);
> +	phb4_write_reg(p, PHB_M64_UPPER_BITS, 0);
>  
>  	/* Init_28 - PHB4 Configuration */
> -	out_be64(p->regs + PHB_PHB4_CONFIG,
> +	phb4_write_reg(p, PHB_PHB4_CONFIG,
>  		 PHB_PHB4C_32BIT_MSI_EN |
>  		 PHB_PHB4C_64BIT_MSI_EN);
>  
>  	/* Init_29 - At least 256ns delay according to spec. Do a dummy
>  	 * read first to flush posted writes
>  	 */
> -	in_be64(p->regs + PHB_PHB4_CONFIG);
> +	phb4_read_reg(p, PHB_PHB4_CONFIG);
>  	time_wait_us(2);
>  
>  	/* Init_30..41 - On-chip IODA tables init */
> @@ -4166,111 +4166,111 @@ static bool phb4_init_rc_cfg(struct phb4 *p)
>  static void phb4_init_errors(struct phb4 *p)
>  {
>  	/* Init_55..63 - PBL errors */
> -	out_be64(p->regs + 0x1900,	0xffffffffffffffffull);
> -	out_be64(p->regs + 0x1908,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x1920,	0x000000004d1780f8ull);
> -	out_be64(p->regs + 0x1928,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x1900,	0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x1908,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x1920,	0x000000004d1780f8ull);
> +	phb4_write_reg(p, 0x1928,	0x0000000000000000ull);
>  	if (p->rev == PHB4_REV_NIMBUS_DD10)
> -		out_be64(p->regs + 0x1930,	0xffffffffb2e87f07ull);
> +		phb4_write_reg(p, 0x1930,	0xffffffffb2e87f07ull);
>  	else
> -		out_be64(p->regs + 0x1930,	0xffffffffb2f87f07ull);
> -	out_be64(p->regs + 0x1940,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x1948,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x1950,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x1958,	0x0000000000000000ull);
> +		phb4_write_reg(p, 0x1930,	0xffffffffb2f87f07ull);
> +	phb4_write_reg(p, 0x1940,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x1948,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x1950,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x1958,	0x0000000000000000ull);
>  
>  	/* Init_64..72 - REGB errors */
> -	out_be64(p->regs + 0x1c00,	0xffffffffffffffffull);
> -	out_be64(p->regs + 0x1c08,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x1c00,	0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x1c08,	0x0000000000000000ull);
>  	/* Enable/disable error status indicators that trigger irqs */
>  	if (p->has_link) {
> -		out_be64(p->regs + 0x1c20,	0x2130006efca8bc00ull);
> -		out_be64(p->regs + 0x1c30,	0xde8fff91035743ffull);
> +		phb4_write_reg(p, 0x1c20,	0x2130006efca8bc00ull);
> +		phb4_write_reg(p, 0x1c30,	0xde8fff91035743ffull);
>  	} else {
> -		out_be64(p->regs + 0x1c20,	0x0000000000000000ull);
> -		out_be64(p->regs + 0x1c30,	0x0000000000000000ull);
> +		phb4_write_reg(p, 0x1c20,	0x0000000000000000ull);
> +		phb4_write_reg(p, 0x1c30,	0x0000000000000000ull);
>  	}
> -	out_be64(p->regs + 0x1c28,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x1c40,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x1c48,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x1c50,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x1c58,	0x0040000000000000ull);
> +	phb4_write_reg(p, 0x1c28,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x1c40,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x1c48,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x1c50,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x1c58,	0x0040000000000000ull);
>  
>  	/* Init_73..81 - TXE errors */
> -	out_be64(p->regs + 0x0d00,	0xffffffffffffffffull);
> -	out_be64(p->regs + 0x0d08,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0d18,	0xffffff0fffffffffull);
> -	out_be64(p->regs + 0x0d28,	0x0000400a00000000ull);
> -	out_be64(p->regs + 0x0d30,	0xdff7fd01f7ddfff0ull); /* XXX CAPI
> has diff. value */
> -	out_be64(p->regs + 0x0d40,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0d48,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0d50,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0d58,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0d00,	0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x0d08,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0d18,	0xffffff0fffffffffull);
> +	phb4_write_reg(p, 0x0d28,	0x0000400a00000000ull);
> +	phb4_write_reg(p, 0x0d30,	0xdff7fd01f7ddfff0ull); /* XXX CAPI
> has diff. value */
> +	phb4_write_reg(p, 0x0d40,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0d48,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0d50,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0d58,	0x0000000000000000ull);
>  
>  	/* Init_82..90 - RXE_ARB errors */
> -	out_be64(p->regs + 0x0d80,	0xffffffffffffffffull);
> -	out_be64(p->regs + 0x0d88,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0d98,	0xfffffffffbffffffull);
> +	phb4_write_reg(p, 0x0d80,	0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x0d88,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0d98,	0xfffffffffbffffffull);
>  	if (p->rev == PHB4_REV_NIMBUS_DD10)
> -		out_be64(p->regs + 0x0da8,	0xc00000b801000060ull);
> +		phb4_write_reg(p, 0x0da8,	0xc00000b801000060ull);
>  	else
> -		out_be64(p->regs + 0x0da8,	0xc00008b801000060ull);
> +		phb4_write_reg(p, 0x0da8,	0xc00008b801000060ull);
>  	/*
>  	 * Errata ER20161123 says we should set the top two bits in
>  	 * 0x0db0 but this causes config space accesses which don't
>  	 * get a response to fence the PHB. This breaks probing,
>  	 * hence we don't set them here.
>  	 */
> -	out_be64(p->regs + 0x0db0,	0x3bffd703fa7fbf8full); /* XXX CAPI
> has diff. value */
> -	out_be64(p->regs + 0x0dc0,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0dc8,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0dd0,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0dd8,	0x0000000004000000ull);
> +	phb4_write_reg(p, 0x0db0,	0x3bffd703fa7fbf8full); /* XXX CAPI
> has diff. value */
> +	phb4_write_reg(p, 0x0dc0,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0dc8,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0dd0,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0dd8,	0x0000000004000000ull);
>  
>  	/* Init_91..99 - RXE_MRG errors */
> -	out_be64(p->regs + 0x0e00,	0xffffffffffffffffull);
> -	out_be64(p->regs + 0x0e08,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0e18,	0xffffffffffffffffull);
> -	out_be64(p->regs + 0x0e28,	0x0000600000000000ull);
> +	phb4_write_reg(p, 0x0e00,	0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x0e08,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0e18,	0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x0e28,	0x0000600000000000ull);
>  	if (p->rev == PHB4_REV_NIMBUS_DD10) /* XXX CAPI has diff. value */
> -		out_be64(p->regs + 0x0e30,	0xffff9effff7fff57ull);
> +		phb4_write_reg(p, 0x0e30,	0xffff9effff7fff57ull);
>  	else
> -		out_be64(p->regs + 0x0e30,	0xfffffeffff7fff57ull);
> -	out_be64(p->regs + 0x0e40,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0e48,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0e50,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0e58,	0x0000000000000000ull);
> +		phb4_write_reg(p, 0x0e30,	0xfffffeffff7fff57ull);
> +	phb4_write_reg(p, 0x0e40,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0e48,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0e50,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0e58,	0x0000000000000000ull);
>  
>  	/* Init_100..108 - RXE_TCE errors */
> -	out_be64(p->regs + 0x0e80,	0xffffffffffffffffull);
> -	out_be64(p->regs + 0x0e88,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0e98,	0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x0e80,	0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x0e88,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0e98,	0xffffffffffffffffull);
>  	if (p->rev == PHB4_REV_NIMBUS_DD10)
> -		out_be64(p->regs + 0x0ea8,	0x6000000000000000ull);
> +		phb4_write_reg(p, 0x0ea8,	0x6000000000000000ull);
>  	else
> -		out_be64(p->regs + 0x0ea8,	0x60000000c0000000ull);
> -	out_be64(p->regs + 0x0eb0,	0x9faeffaf3fffffffull); /* XXX CAPI
> has diff. value */
> -	out_be64(p->regs + 0x0ec0,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0ec8,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0ed0,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0ed8,	0x0000000000000000ull);
> +		phb4_write_reg(p, 0x0ea8,	0x60000000c0000000ull);
> +	phb4_write_reg(p, 0x0eb0,	0x9faeffaf3fffffffull); /* XXX CAPI
> has diff. value */
> +	phb4_write_reg(p, 0x0ec0,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0ec8,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0ed0,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0ed8,	0x0000000000000000ull);
>  
>  	/* Init_109..117 - RXPHB errors */
> -	out_be64(p->regs + 0x0c80,	0xffffffffffffffffull);
> -	out_be64(p->regs + 0x0c88,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0c98,	0xffffffffffffffffull);
> -	out_be64(p->regs + 0x0ca8,	0x0000004000000000ull);
> -	out_be64(p->regs + 0x0cb0,	0x35777033ff000000ull); /* XXX CAPI
> has diff. value */
> -	out_be64(p->regs + 0x0cc0,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0cc8,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0cd0,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0cd8,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0c80,	0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x0c88,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0c98,	0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x0ca8,	0x0000004000000000ull);
> +	phb4_write_reg(p, 0x0cb0,	0x35777033ff000000ull); /* XXX CAPI
> has diff. value */
> +	phb4_write_reg(p, 0x0cc0,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0cc8,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0cd0,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0cd8,	0x0000000000000000ull);
>  
>  	/* Init_118..121 - LEM */
> -	out_be64(p->regs + 0x0c00,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0c30,	0xffffffffffffffffull);
> -	out_be64(p->regs + 0x0c38,	0xffffffffffffffffull);
> -	out_be64(p->regs + 0x0c40,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0c00,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0c30,	0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x0c38,	0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x0c40,	0x0000000000000000ull);
>  }
>  
>  
> @@ -4295,7 +4295,7 @@ static bool phb4_wait_dlp_reset(struct phb4 *p)
>  
>  	PHBDBG(p, "Waiting for DLP PG reset to complete...\n");
>  	for (i = 0; i < DLP_RESET_ATTEMPTS; i++) {
> -		val = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
> +		val = phb4_read_reg(p, PHB_PCIE_DLP_TRAIN_CTL);
>  		if (!(val & PHB_PCIE_DLP_DL_PGRESET))
>  			break;
>  		time_wait_ms(1);
> @@ -4318,40 +4318,40 @@ static void phb4_init_hw(struct phb4 *p, bool
> first_init)
>  	 */
>  
>  	/* Init_2 - Mask FIRs */
> -	out_be64(p->regs + PHB_LEM_ERROR_MASK,			0xfffff
> fffffffffffull);
> +	phb4_write_reg(p, PHB_LEM_ERROR_MASK,			0xffffff
> ffffffffffull);
>  
>  	/* Init_3 - TCE tag enable */
> -	out_be64(p->regs + PHB_TCE_TAG_ENABLE,			0xfffff
> fffffffffffull);
> +	phb4_write_reg(p, PHB_TCE_TAG_ENABLE,			0xffffff
> ffffffffffull);
>  
>  	/* Init_4 - PCIE System Configuration Register
>  	 *
>  	 * Adjust max speed based on system config
>  	 */
> -	val = in_be64(p->regs + PHB_PCIE_SCR);
> +	val = phb4_read_reg(p, PHB_PCIE_SCR);
>  	PHBDBG(p, "Default system config: 0x%016llx\n", val);
>  	val = SETFIELD(PHB_PCIE_SCR_MAXLINKSPEED, val, p->max_link_speed);
> -	out_be64(p->regs + PHB_PCIE_SCR, val);
> +	phb4_write_reg(p, PHB_PCIE_SCR, val);
>  	PHBDBG(p, "New system config    : 0x%016llx\n",
> -	       in_be64(p->regs + PHB_PCIE_SCR));
> +	       phb4_read_reg(p, PHB_PCIE_SCR));
>  
>  	/* Init_5 - deassert CFG reset */
> -	creset = in_be64(p->regs + PHB_PCIE_CRESET);
> +	creset = phb4_read_reg(p, PHB_PCIE_CRESET);
>  	PHBDBG(p, "Initial PHB CRESET is 0x%016llx\n", creset);
>  	creset &= ~PHB_PCIE_CRESET_CFG_CORE;
> -	out_be64(p->regs + PHB_PCIE_CRESET,			creset);
> +	phb4_write_reg(p, PHB_PCIE_CRESET,			creset);
>  
>  	/* Init_6..13 - PCIE DLP Lane EQ control */
>  	if (p->lane_eq) {
> -		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL0, be64_to_cpu(p-
> >lane_eq[0]));
> -		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL1, be64_to_cpu(p-
> >lane_eq[1]));
> -		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL2, be64_to_cpu(p-
> >lane_eq[2]));
> -		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL3, be64_to_cpu(p-
> >lane_eq[3]));
> -		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL20, be64_to_cpu(p-
> >lane_eq[4]));
> -		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL21, be64_to_cpu(p-
> >lane_eq[5]));
> +		phb4_write_reg(p, PHB_PCIE_LANE_EQ_CNTL0, be64_to_cpu(p-
> >lane_eq[0]));
> +		phb4_write_reg(p, PHB_PCIE_LANE_EQ_CNTL1, be64_to_cpu(p-
> >lane_eq[1]));
> +		phb4_write_reg(p, PHB_PCIE_LANE_EQ_CNTL2, be64_to_cpu(p-
> >lane_eq[2]));
> +		phb4_write_reg(p, PHB_PCIE_LANE_EQ_CNTL3, be64_to_cpu(p-
> >lane_eq[3]));
> +		phb4_write_reg(p, PHB_PCIE_LANE_EQ_CNTL20, be64_to_cpu(p-
> >lane_eq[4]));
> +		phb4_write_reg(p, PHB_PCIE_LANE_EQ_CNTL21, be64_to_cpu(p-
> >lane_eq[5]));
>  		if (p->rev == PHB4_REV_NIMBUS_DD10) {
> -			out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL22,
> +			phb4_write_reg(p, PHB_PCIE_LANE_EQ_CNTL22,
>  				 be64_to_cpu(p->lane_eq[6]));
> -			out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL23,
> +			phb4_write_reg(p, PHB_PCIE_LANE_EQ_CNTL23,
>  				 be64_to_cpu(p->lane_eq[7]));
>  		}
>  	}
> @@ -4367,7 +4367,7 @@ static void phb4_init_hw(struct phb4 *p, bool
> first_init)
>  	 */
>  	creset &= ~(PHB_PCIE_CRESET_TLDLP | PHB_PCIE_CRESET_PBL);
>  	creset |= PHB_PCIE_CRESET_PIPE_N;
> -	out_be64(p->regs + PHB_PCIE_CRESET,			   creset)
> ;
> +	phb4_write_reg(p, PHB_PCIE_CRESET,			   creset);
>  
>  	/* Init_16 - Wait for DLP PGRESET to clear */
>  	if (!phb4_wait_dlp_reset(p))
> @@ -4385,16 +4385,16 @@ static void phb4_init_hw(struct phb4 *p, bool
> first_init)
>  	if (!pci_eeh_mmio)
>  		val |= PHB_CTRLR_MMIO_EEH_DISABLE;
>  
> -	out_be64(p->regs + PHB_CTRLR, val);
> +	phb4_write_reg(p, PHB_CTRLR, val);
>  
>  	/* Init_18..41 - Architected IODA3 inits */
>  	phb4_init_ioda3(p);
>  
>  	/* Init_42..45 - Clear DLP error logs */
> -	out_be64(p->regs + 0x1aa0,			0xffffffffffffffffu
> ll);
> -	out_be64(p->regs + 0x1aa8,			0xffffffffffffffffu
> ll);
> -	out_be64(p->regs + 0x1ab0,			0xffffffffffffffffu
> ll);
> -	out_be64(p->regs + 0x1ab8,			0x0);
> +	phb4_write_reg(p, 0x1aa0,			0xfffffffffffffffful
> l);
> +	phb4_write_reg(p, 0x1aa8,			0xfffffffffffffffful
> l);
> +	phb4_write_reg(p, 0x1ab0,			0xfffffffffffffffful
> l);
> +	phb4_write_reg(p, 0x1ab8,			0x0);
>  
>  
>  	/* Init_46..54 : Init root complex config space */
> @@ -4432,30 +4432,30 @@ static void phb4_init_hw(struct phb4 *p, bool
> first_init)
>  			    PCI_CFG_STAT_RECV_PERR);
>  
>  	/* Init_126..130 - Re-enable error interrupts */
> -	out_be64(p->regs + PHB_ERR_IRQ_ENABLE,			0xca888
> 0cc00000000ull);
> -	out_be64(p->regs + PHB_TXE_ERR_IRQ_ENABLE,		0x2008400e0
> 8200000ull);
> -	out_be64(p->regs + PHB_RXE_ARB_ERR_IRQ_ENABLE,		0xc4002
> 8fc01804070ull);
> -	out_be64(p->regs + PHB_RXE_MRG_ERR_IRQ_ENABLE,		0x00006
> 100008000a8ull);
> +	phb4_write_reg(p, PHB_ERR_IRQ_ENABLE,			0xca8880
> cc00000000ull);
> +	phb4_write_reg(p, PHB_TXE_ERR_IRQ_ENABLE,		0x2008400e08
> 200000ull);
> +	phb4_write_reg(p, PHB_RXE_ARB_ERR_IRQ_ENABLE,		0xc40028
> fc01804070ull);
> +	phb4_write_reg(p, PHB_RXE_MRG_ERR_IRQ_ENABLE,		0x000061
> 00008000a8ull);
>  	if (p->rev == PHB4_REV_NIMBUS_DD10)
> -		out_be64(p->regs + PHB_RXE_TCE_ERR_IRQ_ENABLE,	0x60510
> 05000000000ull);
> +		phb4_write_reg(p, PHB_RXE_TCE_ERR_IRQ_ENABLE,	0x605100
> 5000000000ull);
>  	else
> -		out_be64(p->regs + PHB_RXE_TCE_ERR_IRQ_ENABLE,	0x60510
> 050c0000000ull);
> +		phb4_write_reg(p, PHB_RXE_TCE_ERR_IRQ_ENABLE,	0x605100
> 50c0000000ull);
>  
>  	/* Init_131 - Re-enable LEM error mask */
> -	out_be64(p->regs + PHB_LEM_ERROR_MASK,			0x00000
> 00000000000ull);
> +	phb4_write_reg(p, PHB_LEM_ERROR_MASK,			0x000000
> 0000000000ull);
>  
>  
>  	/* Init_132 - Enable DMA address speculation */
> -	out_be64(p->regs + PHB_TCE_SPEC_CTL,			0x0000000
> 000000000ull);
> +	phb4_write_reg(p, PHB_TCE_SPEC_CTL,			0x00000000
> 00000000ull);
>  
>  	/* Init_133 - Timeout Control Register 1 */
> -	out_be64(p->regs + PHB_TIMEOUT_CTRL1,			0x001815
> 0000200000ull);
> +	phb4_write_reg(p, PHB_TIMEOUT_CTRL1,			0x0018150
> 000200000ull);
>  
>  	/* Init_134 - Timeout Control Register 2 */
> -	out_be64(p->regs + PHB_TIMEOUT_CTRL2,			0x000018
> 1700000000ull);
> +	phb4_write_reg(p, PHB_TIMEOUT_CTRL2,			0x0000181
> 700000000ull);
>  
>  	/* Init_135 - PBL Timeout Control Register */
> -	out_be64(p->regs + PHB_PBL_TIMEOUT_CTRL,		0x20150000000
> 00000ull);
> +	phb4_write_reg(p, PHB_PBL_TIMEOUT_CTRL,		0x201500000000
> 0000ull);
>  
>  	/* Mark the PHB as functional which enables all the various sequences
> */
>  	p->state = PHB4_STATE_FUNCTIONAL;
> @@ -4487,7 +4487,7 @@ static bool phb4_read_capabilities(struct phb4 *p)
>  	PHBDBG(p, "Core revision 0x%x\n", p->rev);
>  
>  	/* Read EEH capabilities */
> -	val = in_be64(p->regs + PHB_PHB4_EEH_CAP);
> +	val = phb4_read_reg(p, PHB_PHB4_EEH_CAP);
>  	if (val == 0xffffffffffffffff) {
>  		PHBERR(p, "Failed to read EEH cap, PHB appears broken\n");
>  		return false;
> @@ -4506,7 +4506,7 @@ static bool phb4_read_capabilities(struct phb4 *p)
>  	if (p->rev >= PHB4_REV_NIMBUS_DD20)
>  		p->tvt_size *= 2;
>  
> -	val = in_be64(p->regs + PHB_PHB4_IRQ_CAP);
> +	val = phb4_read_reg(p, PHB_PHB4_IRQ_CAP);
>  	if (val == 0xffffffffffffffff) {
>  		PHBERR(p, "Failed to read IRQ cap, PHB appears broken\n");
>  		return false;
> @@ -4759,9 +4759,9 @@ static int64_t phb4_ndd1_lsi_set_xive(struct irq_source
> *is, uint32_t isn,
>  	 * will go away soon enough.
>  	 */
>  	if (priority == 0xff)
> -		out_be64(p->regs + PHB_IODA_DATA0, IODA3_LIST_Q);
> +		phb4_write_reg(p, PHB_IODA_DATA0, IODA3_LIST_Q);
>  	else {
> -		out_be64(p->regs + PHB_IODA_DATA0, IODA3_LIST_P);
> +		phb4_write_reg(p, PHB_IODA_DATA0, IODA3_LIST_P);
>  		__irq_source_eoi(is, isn);
>  	}
>
Benjamin Herrenschmidt Oct. 3, 2017, 1:49 p.m. | #2
On Mon, 2017-10-02 at 19:23 -0300, Guilherme G. Piccoli wrote:
> Currently, the PHB registers access is mix-performed by the read/write
> primitives or the open coded in/out procedures.
> 
> This patch change all open coded in/outs to use the read/write primitives.
> No functional change is expected.

It adds overhead for registers that are never going to be used via
XSCOM in practice (what would be the point ?)

If you get fenced during some of those init procedures you are pretty
much a goner already. This looks like plaster on a wooden leg to me. 

Care to explain more what you are trying to achieve, it's not clear...

> Signed-off-by: Guilherme G. Piccoli <gpiccoli@linux.vnet.ibm.com>
> ---
>  hw/phb4.c | 418 +++++++++++++++++++++++++++++++-------------------------------
>  1 file changed, 209 insertions(+), 209 deletions(-)
> 
> diff --git a/hw/phb4.c b/hw/phb4.c
> index b94d4925..99902d3a 100644
> --- a/hw/phb4.c
> +++ b/hw/phb4.c
> @@ -480,7 +480,7 @@ static int64_t phb4_pcicfg_read(struct phb4 *p, uint32_t bdfn,
>  			return OPAL_PARAMETER;
>  		}
>  	} else {
> -		out_be64(p->regs + PHB_CONFIG_ADDRESS, addr);
> +		phb4_write_reg(p, PHB_CONFIG_ADDRESS, addr);
>  		switch(size) {
>  		case 1:
>  			*((uint8_t *)data) =
> @@ -559,7 +559,7 @@ static int64_t phb4_pcicfg_write(struct phb4 *p, uint32_t bdfn,
>  		/* We don't support ASB config space writes */
>  		return OPAL_UNSUPPORTED;
>  	} else {
> -		out_be64(p->regs + PHB_CONFIG_ADDRESS, addr);
> +		phb4_write_reg(p, PHB_CONFIG_ADDRESS, addr);
>  		switch(size) {
>  		case 1:

So here you are changing CONFIG_ADDRESS but not CONFIG_DATA ... mind
you SCOM can only do 4 or 8 byte accesses so it wouldn't work anyway,
so I don't see much of a point to this exercise.

>  			out_8(p->regs + PHB_CONFIG_DATA + (offset & 3), data);
> @@ -977,7 +977,7 @@ static int64_t phb4_wait_bit(struct phb4 *p, uint32_t reg,
>  		return OPAL_SUCCESS;
>  
>  	for (;;) {
> -		val = in_be64(p->regs + reg);
> +		val = phb4_read_reg(p, reg);
>  		if (val == 0xffffffffffffffffull) {
>  			/* XXX Fenced ? */
>  			return OPAL_HARDWARE;
> @@ -1035,7 +1035,7 @@ static int64_t phb4_tce_kill(struct phb *phb, uint32_t kill_type,
>  				return OPAL_PARAMETER;
>  			}
>  			/* Perform kill */
> -			out_be64(p->regs + PHB_TCE_KILL, PHB_TCE_KILL_ONE | val);
> +			phb4_write_reg(p, PHB_TCE_KILL, PHB_TCE_KILL_ONE | val);
>  			/* Next page */
>  			dma_addr += tce_size;
>  		}
> @@ -1049,7 +1049,7 @@ static int64_t phb4_tce_kill(struct phb *phb, uint32_t kill_type,
>  		if (rc)
>  			return rc;
>  		/* Perform kill */
> -		out_be64(p->regs + PHB_TCE_KILL, PHB_TCE_KILL_PE |
> +		phb4_write_reg(p, PHB_TCE_KILL, PHB_TCE_KILL_PE |
>  			 SETFIELD(PHB_TCE_KILL_PENUM, 0ull, pe_number));
>  		break;
>  	case OPAL_PCI_TCE_KILL_ALL:
> @@ -1061,14 +1061,14 @@ static int64_t phb4_tce_kill(struct phb *phb, uint32_t kill_type,
>  		if (rc)
>  			return rc;
>  		/* Perform kill */
> -		out_be64(p->regs + PHB_TCE_KILL, PHB_TCE_KILL_ALL);
> +		phb4_write_reg(p, PHB_TCE_KILL, PHB_TCE_KILL_ALL);
>  		break;
>  	default:
>  		return OPAL_PARAMETER;
>  	}
>  
>  	/* Start DMA sync process */
> -	out_be64(p->regs + PHB_DMARD_SYNC, PHB_DMARD_SYNC_START);
> +	phb4_write_reg(p, PHB_DMARD_SYNC, PHB_DMARD_SYNC_START);
>  
>  	/* Wait for kill to complete */
>  	rc = phb4_wait_bit(p, PHB_Q_DMA_R, PHB_Q_DMA_R_TCE_KILL_STATUS, 0);
> @@ -1104,37 +1104,37 @@ static int64_t phb4_ioda_reset(struct phb *phb, bool purge)
>  
>  	/* Init_30..31 - Errata workaround, clear PESTA entry 0 */
>  	phb4_ioda_sel(p, IODA3_TBL_PESTA, 0, false);
> -	out_be64(p->regs + PHB_IODA_DATA0, 0);
> +	phb4_write_reg(p, PHB_IODA_DATA0, 0);
>  
>  	/* Init_32..33 - MIST  */
>  	phb4_ioda_sel(p, IODA3_TBL_MIST, 0, true);
> -	val = in_be64(p->regs + PHB_IODA_ADDR);
> +	val = phb4_read_reg(p, PHB_IODA_ADDR);
>  	val = SETFIELD(PHB_IODA_AD_MIST_PWV, val, 0xf);
> -	out_be64(p->regs + PHB_IODA_ADDR, val);
> +	phb4_write_reg(p, PHB_IODA_ADDR, val);
>  	for (i = 0; i < (p->num_irqs/4); i++)
> -		out_be64(p->regs + PHB_IODA_DATA0, p->mist_cache[i]);
> +		phb4_write_reg(p, PHB_IODA_DATA0, p->mist_cache[i]);
>  
>  	/* Init_34..35 - MRT */
>  	phb4_ioda_sel(p, IODA3_TBL_MRT, 0, true);
>  	for (i = 0; i < p->mrt_size; i++)
> -		out_be64(p->regs + PHB_IODA_DATA0, 0);
> +		phb4_write_reg(p, PHB_IODA_DATA0, 0);
>  
>  	/* Init_36..37 - TVT */
>  	phb4_ioda_sel(p, IODA3_TBL_TVT, 0, true);
>  	for (i = 0; i < p->tvt_size; i++)
> -		out_be64(p->regs + PHB_IODA_DATA0, p->tve_cache[i]);
> +		phb4_write_reg(p, PHB_IODA_DATA0, p->tve_cache[i]);
>  
>  	/* Init_38..39 - MBT */
>  	phb4_ioda_sel(p, IODA3_TBL_MBT, 0, true);
>  	for (i = 0; i < p->mbt_size; i++) {
> -		out_be64(p->regs + PHB_IODA_DATA0, p->mbt_cache[i][0]);
> -		out_be64(p->regs + PHB_IODA_DATA0, p->mbt_cache[i][1]);
> +		phb4_write_reg(p, PHB_IODA_DATA0, p->mbt_cache[i][0]);
> +		phb4_write_reg(p, PHB_IODA_DATA0, p->mbt_cache[i][1]);
>  	}
>  
>  	/* Init_40..41 - MDT */
>  	phb4_ioda_sel(p, IODA3_TBL_MDT, 0, true);
>  	for (i = 0; i < p->max_num_pes; i++)
> -		out_be64(p->regs + PHB_IODA_DATA0, p->mdt_cache[i]);
> +		phb4_write_reg(p, PHB_IODA_DATA0, p->mdt_cache[i]);
>  
>  	/* Additional OPAL specific inits */
>  
> @@ -1147,17 +1147,17 @@ static int64_t phb4_ioda_reset(struct phb *phb, bool purge)
>  	/* Clear PEST & PEEV */
>  	for (i = 0; i < p->max_num_pes; i++) {
>  		phb4_ioda_sel(p, IODA3_TBL_PESTA, i, false);
> -		out_be64(p->regs + PHB_IODA_DATA0, 0);
> +		phb4_write_reg(p, PHB_IODA_DATA0, 0);
>  		phb4_ioda_sel(p, IODA3_TBL_PESTB, i, false);
> -		out_be64(p->regs + PHB_IODA_DATA0, 0);
> +		phb4_write_reg(p, PHB_IODA_DATA0, 0);
>  	}
>  
>  	phb4_ioda_sel(p, IODA3_TBL_PEEV, 0, true);
>  	for (i = 0; i < p->max_num_pes/64; i++)
> -		out_be64(p->regs + PHB_IODA_DATA0, 0);
> +		phb4_write_reg(p, PHB_IODA_DATA0, 0);
>  
>  	/* Invalidate RTE, TCE cache */
> -	out_be64(p->regs + PHB_RTC_INVALIDATE, PHB_RTC_INVALIDATE_ALL);
> +	phb4_write_reg(p, PHB_RTC_INVALIDATE, PHB_RTC_INVALIDATE_ALL);
>  
>  	return phb4_tce_kill(&p->phb, OPAL_PCI_TCE_KILL_ALL, 0, 0, 0, 0);
>  }
> @@ -1173,9 +1173,9 @@ static int64_t phb4_papr_errinjct_reset(struct phb *phb)
>  {
>  	struct phb4 *p = phb_to_phb4(phb);
>  
> -	out_be64(p->regs + PHB_PAPR_ERR_INJ_CTL, 0x0ul);
> -	out_be64(p->regs + PHB_PAPR_ERR_INJ_ADDR, 0x0ul);
> -	out_be64(p->regs + PHB_PAPR_ERR_INJ_MASK, 0x0ul);
> +	phb4_write_reg(p, PHB_PAPR_ERR_INJ_CTL, 0x0ul);
> +	phb4_write_reg(p, PHB_PAPR_ERR_INJ_ADDR, 0x0ul);
> +	phb4_write_reg(p, PHB_PAPR_ERR_INJ_MASK, 0x0ul);
>  
>  	return OPAL_SUCCESS;
>  }
> @@ -1353,8 +1353,8 @@ static int64_t phb4_phb_mmio_enable(struct phb __unused *phb,
>  	p->mbt_cache[window_num][0] = mbt0;
>  	p->mbt_cache[window_num][1] = mbt1;
>  	phb4_ioda_sel(p, IODA3_TBL_MBT, window_num << 1, true);
> -	out_be64(p->regs + PHB_IODA_DATA0, mbt0);
> -	out_be64(p->regs + PHB_IODA_DATA0, mbt1);
> +	phb4_write_reg(p, PHB_IODA_DATA0, mbt0);
> +	phb4_write_reg(p, PHB_IODA_DATA0, mbt1);
>  
>  	return OPAL_SUCCESS;
>  }
> @@ -1404,13 +1404,13 @@ static int64_t phb4_map_pe_mmio_window(struct phb *phb,
>  			p->mdt_cache[segment_num << 1] = mdt0;
>  			p->mdt_cache[(segment_num << 1) + 1] = mdt1;
>  			phb4_ioda_sel(p, IODA3_TBL_MDT, segment_num << 1, true);
> -			out_be64(p->regs + PHB_IODA_DATA0, mdt0);
> -			out_be64(p->regs + PHB_IODA_DATA0, mdt1);
> +			phb4_write_reg(p, PHB_IODA_DATA0, mdt0);
> +			phb4_write_reg(p, PHB_IODA_DATA0, mdt1);
>  		} else {
>  			mdt0 = p->mdt_cache[segment_num];
>  			mdt0 = SETFIELD(IODA3_MDT_PE_A, mdt0, pe_number);
>  			phb4_ioda_sel(p, IODA3_TBL_MDT, segment_num, false);
> -			out_be64(p->regs + PHB_IODA_DATA0, mdt0);
> +			phb4_write_reg(p, PHB_IODA_DATA0, mdt0);
>  		}
>  		break;
>  	case OPAL_M64_WINDOW_TYPE:
> @@ -1471,7 +1471,7 @@ static int64_t phb4_map_pe_dma_window(struct phb *phb,
>  	 */
>  	if (tce_table_size == 0) {
>  		phb4_ioda_sel(p, IODA3_TBL_TVT, window_id, false);
> -		out_be64(p->regs + PHB_IODA_DATA0, 0);
> +		phb4_write_reg(p, PHB_IODA_DATA0, 0);
>  		p->tve_cache[window_id] = 0;
>  		return OPAL_SUCCESS;
>  	}
> @@ -1511,7 +1511,7 @@ static int64_t phb4_map_pe_dma_window(struct phb *phb,
>  	data64 = SETFIELD(IODA3_TVT_NUM_LEVELS, data64, tce_levels - 1);
>  
>  	phb4_ioda_sel(p, IODA3_TBL_TVT, window_id, false);
> -	out_be64(p->regs + PHB_IODA_DATA0, data64);
> +	phb4_write_reg(p, PHB_IODA_DATA0, data64);
>  	p->tve_cache[window_id] = data64;
>  
>  	return OPAL_SUCCESS;
> @@ -1574,7 +1574,7 @@ static int64_t phb4_map_pe_dma_window_real(struct phb *phb,
>  	}
>  
>  	phb4_ioda_sel(p, IODA3_TBL_TVT, window_id, false);
> -	out_be64(p->regs + PHB_IODA_DATA0, tve);
> +	phb4_write_reg(p, PHB_IODA_DATA0, tve);
>  	p->tve_cache[window_id] = tve;
>  
>  	return OPAL_SUCCESS;
> @@ -1608,12 +1608,12 @@ static int64_t phb4_set_ive_pe(struct phb *phb,
>  	/* We need to inject the appropriate MIST write enable bit
>  	 * in the IODA table address register
>  	 */
> -	val = in_be64(p->regs + PHB_IODA_ADDR);
> +	val = phb4_read_reg(p, PHB_IODA_ADDR);
>  	val = SETFIELD(PHB_IODA_AD_MIST_PWV, val, 8 >> mist_quad);
> -	out_be64(p->regs + PHB_IODA_ADDR, val);
> +	phb4_write_reg(p, PHB_IODA_ADDR, val);
>  
>  	/* Write entry */
> -	out_be64(p->regs + PHB_IODA_DATA0, p->mist_cache[mist_idx]);
> +	phb4_write_reg(p, PHB_IODA_DATA0, p->mist_cache[mist_idx]);
>  
>  	return OPAL_SUCCESS;
>  }
> @@ -2074,7 +2074,7 @@ static int64_t phb4_set_pe(struct phb *phb,
>  	}
>  
>  	/* Invalidate the entire RTC */
> -	out_be64(p->regs + PHB_RTC_INVALIDATE, PHB_RTC_INVALIDATE_ALL);
> +	phb4_write_reg(p, PHB_RTC_INVALIDATE, PHB_RTC_INVALIDATE_ALL);
>  
>  	return OPAL_SUCCESS;
>  }
> @@ -2135,15 +2135,15 @@ static void phb4_prepare_link_change(struct pci_slot *slot, bool is_up)
>  		p->flags &= ~PHB4_CFG_BLOCKED;
>  
>  		/* Re-enable link down errors */
> -		out_be64(p->regs + PHB_PCIE_MISC_STRAP,
> +		phb4_write_reg(p, PHB_PCIE_MISC_STRAP,
>  			 0x0000060000000000ull);
>  
>  		/* Re-enable error status indicators that trigger irqs */
> -		out_be64(p->regs + PHB_REGB_ERR_INF_ENABLE,
> +		phb4_write_reg(p, PHB_REGB_ERR_INF_ENABLE,
>  			 0x2130006efca8bc00ull);
> -		out_be64(p->regs + PHB_REGB_ERR_ERC_ENABLE,
> +		phb4_write_reg(p, PHB_REGB_ERR_ERC_ENABLE,
>  			 0x0000000000000000ull);
> -		out_be64(p->regs + PHB_REGB_ERR_FAT_ENABLE,
> +		phb4_write_reg(p, PHB_REGB_ERR_FAT_ENABLE,
>  			 0xde8fff91035743ffull);
>  
>  		/*
> @@ -2167,12 +2167,12 @@ static void phb4_prepare_link_change(struct pci_slot *slot, bool is_up)
>  				    PCIECAP_AER_CE_MASK, reg32);
>  
>  		/* Clear error link enable & error link down kill enable */
> -		out_be64(p->regs + PHB_PCIE_MISC_STRAP, 0);
> +		phb4_write_reg(p, PHB_PCIE_MISC_STRAP, 0);
>  
>  		/* Disable all error status indicators that trigger irqs */
> -		out_be64(p->regs + PHB_REGB_ERR_INF_ENABLE, 0);
> -		out_be64(p->regs + PHB_REGB_ERR_ERC_ENABLE, 0);
> -		out_be64(p->regs + PHB_REGB_ERR_FAT_ENABLE, 0);
> +		phb4_write_reg(p, PHB_REGB_ERR_INF_ENABLE, 0);
> +		phb4_write_reg(p, PHB_REGB_ERR_ERC_ENABLE, 0);
> +		phb4_write_reg(p, PHB_REGB_ERR_FAT_ENABLE, 0);
>  
>  		/* Block PCI-CFG access */
>  		p->flags |= PHB4_CFG_BLOCKED;
> @@ -2189,7 +2189,7 @@ static int64_t phb4_get_presence_state(struct pci_slot *slot, uint8_t *val)
>  		return OPAL_HARDWARE;
>  
>  	/* Check hotplug status */
> -	hps = in_be64(p->regs + PHB_PCIE_HOTPLUG_STATUS);
> +	hps = phb4_read_reg(p, PHB_PCIE_HOTPLUG_STATUS);
>  	if (!(hps & PHB_PCIE_HPSTAT_PRESENCE)) {
>  		*val = OPAL_PCI_SLOT_PRESENT;
>  	} else {
> @@ -2198,7 +2198,7 @@ static int64_t phb4_get_presence_state(struct pci_slot *slot, uint8_t *val)
>  		 * we are on a broken simulation environment and still
>  		 * return a valid presence. Otherwise, not present.
>  		 */
> -		dtctl = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
> +		dtctl = phb4_read_reg(p, PHB_PCIE_DLP_TRAIN_CTL);
>  		if (dtctl & PHB_PCIE_DLP_TL_LINKACT) {
>  			PHBERR(p, "Presence detect 0 but link set !\n");
>  			*val = OPAL_PCI_SLOT_PRESENT;
> @@ -2220,7 +2220,7 @@ static int64_t phb4_get_link_info(struct pci_slot *slot, uint8_t *speed,
>  	uint8_t s;
>  
>  	/* Link is up, let's find the actual speed */
> -	reg = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
> +	reg = phb4_read_reg(p, PHB_PCIE_DLP_TRAIN_CTL);
>  	if (!(reg & PHB_PCIE_DLP_TL_LINKACT)) {
>  		*width = 0;
>  		if (speed)
> @@ -2350,7 +2350,7 @@ static bool phb4_fenced(struct phb4 *p)
>  	 * An all 1's from the PHB indicates a PHB freeze/fence. We
>  	 * don't really differenciate them at this point.
>  	 */
> -	if (in_be64(p->regs + PHB_CPU_LOADSTORE_STATUS)!= 0xfffffffffffffffful)
> +	if (phb4_read_reg(p, PHB_CPU_LOADSTORE_STATUS)!= 0xfffffffffffffffful)
>  		return false;
>  
>  	PHBERR(p, "PHB Freeze/Fence detected !\n");
> @@ -2529,7 +2529,7 @@ static void phb4_training_trace(struct phb4 *p)
>  
>  	while(1) {
>  		now = mftb();
> -		reg = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
> +		reg = phb4_read_reg(p, PHB_PCIE_DLP_TRAIN_CTL);
>  		if (reg != reglast)
>  			phb4_train_info(p, reg, now - start);
>  		reglast = reg;
> @@ -2573,7 +2573,7 @@ static int64_t phb4_poll_link(struct pci_slot *slot)
>  		 * because simics doesn't seem to implement the electrical
>  		 * link bit at all
>  		 */
> -		reg = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
> +		reg = phb4_read_reg(p, PHB_PCIE_DLP_TRAIN_CTL);
>  		if (!phb4_check_reg(p, reg)) {
>  			PHBERR(p, "PHB fence waiting for electrical link\n");
>  			return phb4_retry_state(slot);
> @@ -2596,7 +2596,7 @@ static int64_t phb4_poll_link(struct pci_slot *slot)
>  		/* Retry */
>  		return pci_slot_set_sm_timeout(slot, msecs_to_tb(10));
>  	case PHB4_SLOT_LINK_WAIT:
> -		reg = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
> +		reg = phb4_read_reg(p, PHB_PCIE_DLP_TRAIN_CTL);
>  		if (!phb4_check_reg(p, reg)) {
>  			PHBERR(p, "LINK: PHB fence waiting for link training\n");
>  			return phb4_retry_state(slot);
> @@ -2621,7 +2621,7 @@ static int64_t phb4_poll_link(struct pci_slot *slot)
>  			PHBERR(p, "LINK: PHB fenced waiting for stabilty\n");
>  			return phb4_retry_state(slot);
>  		}
> -		reg = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
> +		reg = phb4_read_reg(p, PHB_PCIE_DLP_TRAIN_CTL);
>  		if (!phb4_check_reg(p, reg)) {
>  			PHBERR(p, "LINK: PHB fence reading training control\n");
>  			return phb4_retry_state(slot);
> @@ -2736,9 +2736,9 @@ static int64_t phb4_freset(struct pci_slot *slot)
>  	case PHB4_SLOT_FRESET_START:
>  		if (!p->skip_perst) {
>  			PHBDBG(p, "FRESET: Assert\n");
> -			reg = in_be64(p->regs + PHB_PCIE_CRESET);
> +			reg = phb4_read_reg(p, PHB_PCIE_CRESET);
>  			reg &= ~PHB_PCIE_CRESET_PERST_N;
> -			out_be64(p->regs + PHB_PCIE_CRESET, reg);
> +			phb4_write_reg(p, PHB_PCIE_CRESET, reg);
>  			pci_slot_set_state(slot,
>  				PHB4_SLOT_FRESET_ASSERT_DELAY);
>  			/* 250ms assert time aligns with powernv */
> @@ -2756,15 +2756,15 @@ static int64_t phb4_freset(struct pci_slot *slot)
>  
>  		if (pci_tracing) {
>  			/* Enable tracing */
> -			reg = in_be64(p->regs + PHB_PCIE_DLP_TRWCTL);
> -			out_be64(p->regs + PHB_PCIE_DLP_TRWCTL,
> +			reg = phb4_read_reg(p, PHB_PCIE_DLP_TRWCTL);
> +			phb4_write_reg(p, PHB_PCIE_DLP_TRWCTL,
>  				 reg | PHB_PCIE_DLP_TRWCTL_EN);
>  		}
>  
>  		PHBDBG(p, "FRESET: Deassert\n");
> -		reg = in_be64(p->regs + PHB_PCIE_CRESET);
> +		reg = phb4_read_reg(p, PHB_PCIE_CRESET);
>  		reg |= PHB_PCIE_CRESET_PERST_N;
> -		out_be64(p->regs + PHB_PCIE_CRESET, reg);
> +		phb4_write_reg(p, PHB_PCIE_CRESET, reg);
>  		pci_slot_set_state(slot,
>  			PHB4_SLOT_FRESET_DEASSERT_DELAY);
>  
> @@ -3002,7 +3002,7 @@ static int64_t phb4_eeh_freeze_status(struct phb *phb, uint64_t pe_number,
>  
>  	/* Check the PEEV */
>  	phb4_ioda_sel(p, IODA3_TBL_PEEV, pe_number / 64, false);
> -	peev = in_be64(p->regs + PHB_IODA_DATA0);
> +	peev = phb4_read_reg(p, PHB_IODA_DATA0);
>  	if (!(peev & peev_bit))
>  		return OPAL_SUCCESS;
>  
> @@ -3013,9 +3013,9 @@ static int64_t phb4_eeh_freeze_status(struct phb *phb, uint64_t pe_number,
>  
>  	/* Read the PESTA & PESTB */
>  	phb4_ioda_sel(p, IODA3_TBL_PESTA, pe_number, false);
> -	pesta = in_be64(p->regs + PHB_IODA_DATA0);
> +	pesta = phb4_read_reg(p, PHB_IODA_DATA0);
>  	phb4_ioda_sel(p, IODA3_TBL_PESTB, pe_number, false);
> -	pestb = in_be64(p->regs + PHB_IODA_DATA0);
> +	pestb = phb4_read_reg(p, PHB_IODA_DATA0);
>  
>  	/* Convert them */
>  	if (pesta & IODA3_PESTA_MMIO_FROZEN)
> @@ -3045,7 +3045,7 @@ static int64_t phb4_eeh_freeze_clear(struct phb *phb, uint64_t pe_number,
>  	 * contain a freeze state from a previous error or simply set
>  	 * explicitely by the user
>  	 */
> -	err = in_be64(p->regs + PHB_ETU_ERR_SUMMARY);
> +	err = phb4_read_reg(p, PHB_ETU_ERR_SUMMARY);
>  	if (err == 0xffffffffffffffff) {
>  		if (phb4_fenced(p)) {
>  			PHBERR(p, "eeh_freeze_clear on fenced PHB\n");
> @@ -3061,18 +3061,18 @@ static int64_t phb4_eeh_freeze_clear(struct phb *phb, uint64_t pe_number,
>  	 */
>  	if (eeh_action_token & OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO) {
>  		phb4_ioda_sel(p, IODA3_TBL_PESTA, pe_number, false);
> -		out_be64(p->regs + PHB_IODA_DATA0, 0);
> +		phb4_write_reg(p, PHB_IODA_DATA0, 0);
>  	}
>  	if (eeh_action_token & OPAL_EEH_ACTION_CLEAR_FREEZE_DMA) {
>  		phb4_ioda_sel(p, IODA3_TBL_PESTB, pe_number, false);
> -		out_be64(p->regs + PHB_IODA_DATA0, 0);
> +		phb4_write_reg(p, PHB_IODA_DATA0, 0);
>  	}
>  
>  
>  	/* Update ER pending indication */
>  	phb4_ioda_sel(p, IODA3_TBL_PEEV, 0, true);
>  	for (i = 0; i < p->num_pes/64; i++) {
> -		peev = in_be64(p->regs + PHB_IODA_DATA0);
> +		peev = phb4_read_reg(p, PHB_IODA_DATA0);
>  		if (peev) {
>  			frozen_pe = true;
>  			break;
> @@ -3108,16 +3108,16 @@ static int64_t phb4_eeh_freeze_set(struct phb *phb, uint64_t pe_number,
>  
>  	if (eeh_action_token & OPAL_EEH_ACTION_SET_FREEZE_MMIO) {
>  		phb4_ioda_sel(p, IODA3_TBL_PESTA, pe_number, false);
> -		data = in_be64(p->regs + PHB_IODA_DATA0);
> +		data = phb4_read_reg(p, PHB_IODA_DATA0);
>  		data |= IODA3_PESTA_MMIO_FROZEN;
> -		out_be64(p->regs + PHB_IODA_DATA0, data);
> +		phb4_write_reg(p, PHB_IODA_DATA0, data);
>  	}
>  
>  	if (eeh_action_token & OPAL_EEH_ACTION_SET_FREEZE_DMA) {
>  		phb4_ioda_sel(p, IODA3_TBL_PESTB, pe_number, false);
> -		data = in_be64(p->regs + PHB_IODA_DATA0);
> +		data = phb4_read_reg(p, PHB_IODA_DATA0);
>  		data |= IODA3_PESTB_DMA_STOPPED;
> -		out_be64(p->regs + PHB_IODA_DATA0, data);
> +		phb4_write_reg(p, PHB_IODA_DATA0, data);
>  	}
>  
>  	return OPAL_SUCCESS;
> @@ -3165,7 +3165,7 @@ static int64_t phb4_eeh_next_error(struct phb *phb,
>  	if (!phb4_err_pending(p)) {
>  		phb4_ioda_sel(p, IODA3_TBL_PEEV, 0, true);
>  		for (i = 0; i < peev_size; i++) {
> -			peev = in_be64(p->regs + PHB_IODA_DATA0);
> +			peev = phb4_read_reg(p, PHB_IODA_DATA0);
>  			if (peev) {
>  				p->err.err_src	 = PHB4_ERR_SRC_PHB;
>  				p->err.err_class = PHB4_ERR_CLASS_ER;
> @@ -3211,7 +3211,7 @@ static int64_t phb4_eeh_next_error(struct phb *phb,
>  
>  			for (i = peev_size - 1; i >= 0; i--) {
>  				phb4_ioda_sel(p, IODA3_TBL_PEEV, i, false);
> -				peev = in_be64(p->regs + PHB_IODA_DATA0);
> +				peev = phb4_read_reg(p, PHB_IODA_DATA0);
>  				for (j = 0; j < 64; j++) {
>  					if (peev & PPC_BIT(j)) {
>  						*first_frozen_pe = i * 64 + j;
> @@ -3254,9 +3254,9 @@ static int64_t phb4_err_inject_finalize(struct phb4 *phb, uint64_t addr,
>  	else
>  		ctrl |= PHB_PAPR_ERR_INJ_CTL_RD;
>  
> -	out_be64(phb->regs + PHB_PAPR_ERR_INJ_ADDR, addr);
> -	out_be64(phb->regs + PHB_PAPR_ERR_INJ_MASK, mask);
> -	out_be64(phb->regs + PHB_PAPR_ERR_INJ_CTL, ctrl);
> +	phb4_write_reg(phb, PHB_PAPR_ERR_INJ_ADDR,	addr);
> +	phb4_write_reg(phb, PHB_PAPR_ERR_INJ_MASK,	mask);
> +	phb4_write_reg(phb, PHB_PAPR_ERR_INJ_CTL,	ctrl);
>  
>  	return OPAL_SUCCESS;
>  }
> @@ -3376,7 +3376,7 @@ static int64_t phb4_err_inject(struct phb *phb, uint64_t pe_number,
>  		return OPAL_PARAMETER;
>  
>  	/* Clear leftover from last time */
> -	out_be64(p->regs + PHB_PAPR_ERR_INJ_CTL, 0x0ul);
> +	phb4_write_reg(p, PHB_PAPR_ERR_INJ_CTL, 0x0ul);
>  
>  	switch (func) {
>  	case OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR:
> @@ -3628,19 +3628,19 @@ static void phb4_init_capp_regs(struct phb4 *p)
>  static void phb4_init_capp_errors(struct phb4 *p)
>  {
>  	/* Init_77: TXE Error AIB Fence Enable Register */
> -	out_be64(p->regs + 0x0d30,	0xdff7ff0bf7ddfff0ull);
> +	phb4_write_reg(p, 0x0d30,	0xdff7ff0bf7ddfff0ull);
>  
>  	/* Init_86: RXE_ARB Error AIB Fence Enable Register */
> -	out_be64(p->regs + 0x0db0,	0xfbffd7bbfb7fbfefull);
> +	phb4_write_reg(p, 0x0db0,	0xfbffd7bbfb7fbfefull);
>  
>  	/* Init_95: RXE_MRG Error AIB Fence Enable Register */
> -	out_be64(p->regs + 0x0e30,	0xfffffeffff7fff57ull);
> +	phb4_write_reg(p, 0x0e30,	0xfffffeffff7fff57ull);
>  
>  	/* Init_104: RXE_TCE Error AIB Fence Enable Register */
> -	out_be64(p->regs + 0x0eb0,	0xffaeffafffffffffull);
> +	phb4_write_reg(p, 0x0eb0,	0xffaeffafffffffffull);
>  
>  	/* Init_113: PHB Error AIB Fence Enable Register */
> -	out_be64(p->regs + 0x0cb0,	0x35777073ff000000ull);
> +	phb4_write_reg(p, 0x0cb0,	0x35777073ff000000ull);
>  }
>  
>  /* Power Bus Common Queue Registers
> @@ -3731,12 +3731,12 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number,
>  	 * Bit [0:7] XSL_DSNCTL[capiind]
>  	 * Init_25 - CAPI Compare/Mask
>  	 */
> -	out_be64(p->regs + PHB_CAPI_CMPM,
> +	phb4_write_reg(p, PHB_CAPI_CMPM,
>  		 0x0200FE0000000000Ull | PHB_CAPI_CMPM_ENABLE);
>  
>  	if (!(p->rev == PHB4_REV_NIMBUS_DD10)) {
>  		/* Init_24 - ASN Compare/Mask */
> -		out_be64(p->regs + PHB_PBL_ASN_CMPM,
> +		phb4_write_reg(p, PHB_PBL_ASN_CMPM,
>  			 0x0400FF0000000000Ull | PHB_PBL_ASN_ENABLE);
>  
>  		/* PBCQ Tunnel Bar Register
> @@ -3761,7 +3761,7 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number,
>  	}
>  
>  	/* non-translate/50-bit mode */
> -	out_be64(p->regs + PHB_NXLATE_PREFIX, 0x0000000000000000Ull);
> +	phb4_write_reg(p, PHB_NXLATE_PREFIX, 0x0000000000000000Ull);
>  
>  	/* set tve no translate mode allow mmio window */
>  	memset(p->tve_cache, 0x0, sizeof(p->tve_cache));
> @@ -3800,7 +3800,7 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number,
>  
>  	phb4_ioda_sel(p, IODA3_TBL_TVT, 0, true);
>  	for (i = 0; i < p->tvt_size; i++)
> -		out_be64(p->regs + PHB_IODA_DATA0, p->tve_cache[i]);
> +		phb4_write_reg(p, PHB_IODA_DATA0, p->tve_cache[i]);
>  
>  	/* set mbt bar to pass capi mmio window. First applied cleared
>  	 * values to HW
> @@ -3811,8 +3811,8 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number,
>  	}
>  	phb4_ioda_sel(p, IODA3_TBL_MBT, 0, true);
>  	for (i = 0; i < p->mbt_size; i++) {
> -		out_be64(p->regs + PHB_IODA_DATA0, p->mbt_cache[i][0]);
> -		out_be64(p->regs + PHB_IODA_DATA0, p->mbt_cache[i][1]);
> +		phb4_write_reg(p, PHB_IODA_DATA0, p->mbt_cache[i][0]);
> +		phb4_write_reg(p, PHB_IODA_DATA0, p->mbt_cache[i][1]);
>  	}
>  
>  	p->mbt_cache[0][0] = IODA3_MBT0_ENABLE |
> @@ -3835,8 +3835,8 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number,
>  
>  	phb4_ioda_sel(p, IODA3_TBL_MBT, 0, true);
>  	for (i = 0; i < p->mbt_size; i++) {
> -		out_be64(p->regs + PHB_IODA_DATA0, p->mbt_cache[i][0]);
> -		out_be64(p->regs + PHB_IODA_DATA0, p->mbt_cache[i][1]);
> +		phb4_write_reg(p, PHB_IODA_DATA0, p->mbt_cache[i][0]);
> +		phb4_write_reg(p, PHB_IODA_DATA0, p->mbt_cache[i][1]);
>  	}
>  
>  	phb4_init_capp_errors(p);
> @@ -3923,7 +3923,7 @@ static void phb4_p2p_set_initiator(struct phb4 *p, uint16_t pe_number)
>  	PHBDBG(p, "Setting TVE#1 for peer-to-peer for pe %d\n", pe_number);
>  	tve = PPC_BIT(51);
>  	phb4_ioda_sel(p, IODA3_TBL_TVT, window_id, false);
> -	out_be64(p->regs + PHB_IODA_DATA0, tve);
> +	phb4_write_reg(p, PHB_IODA_DATA0, tve);
>  	p->tve_cache[window_id] = tve;
>  }
>  
> @@ -4027,29 +4027,29 @@ static const struct phb_ops phb4_ops = {
>  static void phb4_init_ioda3(struct phb4 *p)
>  {
>  	/* Init_18 - Interrupt Notify Base Address */
> -	out_be64(p->regs + PHB_INT_NOTIFY_ADDR, p->irq_port);
> +	phb4_write_reg(p, PHB_INT_NOTIFY_ADDR, p->irq_port);
>  
>  	/* Init_19 - Interrupt Notify Base Index */
> -	out_be64(p->regs + PHB_INT_NOTIFY_INDEX,
> +	phb4_write_reg(p, PHB_INT_NOTIFY_INDEX,
>  		 xive_get_notify_base(p->base_msi));
>  
>  	/* Init_19x - Not in spec: Initialize source ID */
>  	PHBDBG(p, "Reset state SRC_ID: %016llx\n",
> -	       in_be64(p->regs + PHB_LSI_SOURCE_ID));
> -	out_be64(p->regs + PHB_LSI_SOURCE_ID,
> +	       phb4_read_reg(p, PHB_LSI_SOURCE_ID));
> +	phb4_write_reg(p, PHB_LSI_SOURCE_ID,
>  		 SETFIELD(PHB_LSI_SRC_ID, 0ull, (p->num_irqs - 1) >> 3));
>  
>  	/* Init_20 - RTT BAR */
> -	out_be64(p->regs + PHB_RTT_BAR, p->tbl_rtt | PHB_RTT_BAR_ENABLE);
> +	phb4_write_reg(p, PHB_RTT_BAR, p->tbl_rtt | PHB_RTT_BAR_ENABLE);
>  
>  	/* Init_21 - PELT-V BAR */
> -	out_be64(p->regs + PHB_PELTV_BAR, p->tbl_peltv | PHB_PELTV_BAR_ENABLE);
> +	phb4_write_reg(p, PHB_PELTV_BAR, p->tbl_peltv | PHB_PELTV_BAR_ENABLE);
>  
>  	/* Init_22 - Setup M32 starting address */
> -	out_be64(p->regs + PHB_M32_START_ADDR, M32_PCI_START);
> +	phb4_write_reg(p, PHB_M32_START_ADDR, M32_PCI_START);
>  
>  	/* Init_23 - Setup PEST BAR */
> -	out_be64(p->regs + PHB_PEST_BAR,
> +	phb4_write_reg(p, PHB_PEST_BAR,
>  		 p->tbl_pest | PHB_PEST_BAR_ENABLE);
>  
>  	/* Init_24 - CRW Base Address Reg */
> @@ -4062,17 +4062,17 @@ static void phb4_init_ioda3(struct phb4 *p)
>  	/* See enable_capi_mode() */
>  
>  	/* Init_27 - PCIE Outbound upper address */
> -	out_be64(p->regs + PHB_M64_UPPER_BITS, 0);
> +	phb4_write_reg(p, PHB_M64_UPPER_BITS, 0);
>  
>  	/* Init_28 - PHB4 Configuration */
> -	out_be64(p->regs + PHB_PHB4_CONFIG,
> +	phb4_write_reg(p, PHB_PHB4_CONFIG,
>  		 PHB_PHB4C_32BIT_MSI_EN |
>  		 PHB_PHB4C_64BIT_MSI_EN);
>  
>  	/* Init_29 - At least 256ns delay according to spec. Do a dummy
>  	 * read first to flush posted writes
>  	 */
> -	in_be64(p->regs + PHB_PHB4_CONFIG);
> +	phb4_read_reg(p, PHB_PHB4_CONFIG);
>  	time_wait_us(2);
>  
>  	/* Init_30..41 - On-chip IODA tables init */
> @@ -4166,111 +4166,111 @@ static bool phb4_init_rc_cfg(struct phb4 *p)
>  static void phb4_init_errors(struct phb4 *p)
>  {
>  	/* Init_55..63 - PBL errors */
> -	out_be64(p->regs + 0x1900,	0xffffffffffffffffull);
> -	out_be64(p->regs + 0x1908,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x1920,	0x000000004d1780f8ull);
> -	out_be64(p->regs + 0x1928,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x1900,	0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x1908,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x1920,	0x000000004d1780f8ull);
> +	phb4_write_reg(p, 0x1928,	0x0000000000000000ull);
>  	if (p->rev == PHB4_REV_NIMBUS_DD10)
> -		out_be64(p->regs + 0x1930,	0xffffffffb2e87f07ull);
> +		phb4_write_reg(p, 0x1930,	0xffffffffb2e87f07ull);
>  	else
> -		out_be64(p->regs + 0x1930,	0xffffffffb2f87f07ull);
> -	out_be64(p->regs + 0x1940,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x1948,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x1950,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x1958,	0x0000000000000000ull);
> +		phb4_write_reg(p, 0x1930,	0xffffffffb2f87f07ull);
> +	phb4_write_reg(p, 0x1940,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x1948,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x1950,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x1958,	0x0000000000000000ull);
>  
>  	/* Init_64..72 - REGB errors */
> -	out_be64(p->regs + 0x1c00,	0xffffffffffffffffull);
> -	out_be64(p->regs + 0x1c08,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x1c00,	0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x1c08,	0x0000000000000000ull);
>  	/* Enable/disable error status indicators that trigger irqs */
>  	if (p->has_link) {
> -		out_be64(p->regs + 0x1c20,	0x2130006efca8bc00ull);
> -		out_be64(p->regs + 0x1c30,	0xde8fff91035743ffull);
> +		phb4_write_reg(p, 0x1c20,	0x2130006efca8bc00ull);
> +		phb4_write_reg(p, 0x1c30,	0xde8fff91035743ffull);
>  	} else {
> -		out_be64(p->regs + 0x1c20,	0x0000000000000000ull);
> -		out_be64(p->regs + 0x1c30,	0x0000000000000000ull);
> +		phb4_write_reg(p, 0x1c20,	0x0000000000000000ull);
> +		phb4_write_reg(p, 0x1c30,	0x0000000000000000ull);
>  	}
> -	out_be64(p->regs + 0x1c28,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x1c40,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x1c48,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x1c50,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x1c58,	0x0040000000000000ull);
> +	phb4_write_reg(p, 0x1c28,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x1c40,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x1c48,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x1c50,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x1c58,	0x0040000000000000ull);
>  
>  	/* Init_73..81 - TXE errors */
> -	out_be64(p->regs + 0x0d00,	0xffffffffffffffffull);
> -	out_be64(p->regs + 0x0d08,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0d18,	0xffffff0fffffffffull);
> -	out_be64(p->regs + 0x0d28,	0x0000400a00000000ull);
> -	out_be64(p->regs + 0x0d30,	0xdff7fd01f7ddfff0ull); /* XXX CAPI has diff. value */
> -	out_be64(p->regs + 0x0d40,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0d48,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0d50,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0d58,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0d00,	0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x0d08,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0d18,	0xffffff0fffffffffull);
> +	phb4_write_reg(p, 0x0d28,	0x0000400a00000000ull);
> +	phb4_write_reg(p, 0x0d30,	0xdff7fd01f7ddfff0ull); /* XXX CAPI has diff. value */
> +	phb4_write_reg(p, 0x0d40,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0d48,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0d50,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0d58,	0x0000000000000000ull);
>  
>  	/* Init_82..90 - RXE_ARB errors */
> -	out_be64(p->regs + 0x0d80,	0xffffffffffffffffull);
> -	out_be64(p->regs + 0x0d88,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0d98,	0xfffffffffbffffffull);
> +	phb4_write_reg(p, 0x0d80,	0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x0d88,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0d98,	0xfffffffffbffffffull);
>  	if (p->rev == PHB4_REV_NIMBUS_DD10)
> -		out_be64(p->regs + 0x0da8,	0xc00000b801000060ull);
> +		phb4_write_reg(p, 0x0da8,	0xc00000b801000060ull);
>  	else
> -		out_be64(p->regs + 0x0da8,	0xc00008b801000060ull);
> +		phb4_write_reg(p, 0x0da8,	0xc00008b801000060ull);
>  	/*
>  	 * Errata ER20161123 says we should set the top two bits in
>  	 * 0x0db0 but this causes config space accesses which don't
>  	 * get a response to fence the PHB. This breaks probing,
>  	 * hence we don't set them here.
>  	 */
> -	out_be64(p->regs + 0x0db0,	0x3bffd703fa7fbf8full); /* XXX CAPI has diff. value */
> -	out_be64(p->regs + 0x0dc0,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0dc8,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0dd0,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0dd8,	0x0000000004000000ull);
> +	phb4_write_reg(p, 0x0db0,	0x3bffd703fa7fbf8full); /* XXX CAPI has diff. value */
> +	phb4_write_reg(p, 0x0dc0,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0dc8,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0dd0,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0dd8,	0x0000000004000000ull);
>  
>  	/* Init_91..99 - RXE_MRG errors */
> -	out_be64(p->regs + 0x0e00,	0xffffffffffffffffull);
> -	out_be64(p->regs + 0x0e08,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0e18,	0xffffffffffffffffull);
> -	out_be64(p->regs + 0x0e28,	0x0000600000000000ull);
> +	phb4_write_reg(p, 0x0e00,	0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x0e08,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0e18,	0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x0e28,	0x0000600000000000ull);
>  	if (p->rev == PHB4_REV_NIMBUS_DD10) /* XXX CAPI has diff. value */
> -		out_be64(p->regs + 0x0e30,	0xffff9effff7fff57ull);
> +		phb4_write_reg(p, 0x0e30,	0xffff9effff7fff57ull);
>  	else
> -		out_be64(p->regs + 0x0e30,	0xfffffeffff7fff57ull);
> -	out_be64(p->regs + 0x0e40,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0e48,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0e50,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0e58,	0x0000000000000000ull);
> +		phb4_write_reg(p, 0x0e30,	0xfffffeffff7fff57ull);
> +	phb4_write_reg(p, 0x0e40,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0e48,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0e50,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0e58,	0x0000000000000000ull);
>  
>  	/* Init_100..108 - RXE_TCE errors */
> -	out_be64(p->regs + 0x0e80,	0xffffffffffffffffull);
> -	out_be64(p->regs + 0x0e88,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0e98,	0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x0e80,	0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x0e88,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0e98,	0xffffffffffffffffull);
>  	if (p->rev == PHB4_REV_NIMBUS_DD10)
> -		out_be64(p->regs + 0x0ea8,	0x6000000000000000ull);
> +		phb4_write_reg(p, 0x0ea8,	0x6000000000000000ull);
>  	else
> -		out_be64(p->regs + 0x0ea8,	0x60000000c0000000ull);
> -	out_be64(p->regs + 0x0eb0,	0x9faeffaf3fffffffull); /* XXX CAPI has diff. value */
> -	out_be64(p->regs + 0x0ec0,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0ec8,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0ed0,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0ed8,	0x0000000000000000ull);
> +		phb4_write_reg(p, 0x0ea8,	0x60000000c0000000ull);
> +	phb4_write_reg(p, 0x0eb0,	0x9faeffaf3fffffffull); /* XXX CAPI has diff. value */
> +	phb4_write_reg(p, 0x0ec0,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0ec8,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0ed0,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0ed8,	0x0000000000000000ull);
>  
>  	/* Init_109..117 - RXPHB errors */
> -	out_be64(p->regs + 0x0c80,	0xffffffffffffffffull);
> -	out_be64(p->regs + 0x0c88,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0c98,	0xffffffffffffffffull);
> -	out_be64(p->regs + 0x0ca8,	0x0000004000000000ull);
> -	out_be64(p->regs + 0x0cb0,	0x35777033ff000000ull); /* XXX CAPI has diff. value */
> -	out_be64(p->regs + 0x0cc0,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0cc8,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0cd0,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0cd8,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0c80,	0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x0c88,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0c98,	0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x0ca8,	0x0000004000000000ull);
> +	phb4_write_reg(p, 0x0cb0,	0x35777033ff000000ull); /* XXX CAPI has diff. value */
> +	phb4_write_reg(p, 0x0cc0,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0cc8,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0cd0,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0cd8,	0x0000000000000000ull);
>  
>  	/* Init_118..121 - LEM */
> -	out_be64(p->regs + 0x0c00,	0x0000000000000000ull);
> -	out_be64(p->regs + 0x0c30,	0xffffffffffffffffull);
> -	out_be64(p->regs + 0x0c38,	0xffffffffffffffffull);
> -	out_be64(p->regs + 0x0c40,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0c00,	0x0000000000000000ull);
> +	phb4_write_reg(p, 0x0c30,	0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x0c38,	0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x0c40,	0x0000000000000000ull);
>  }
>  
>  
> @@ -4295,7 +4295,7 @@ static bool phb4_wait_dlp_reset(struct phb4 *p)
>  
>  	PHBDBG(p, "Waiting for DLP PG reset to complete...\n");
>  	for (i = 0; i < DLP_RESET_ATTEMPTS; i++) {
> -		val = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
> +		val = phb4_read_reg(p, PHB_PCIE_DLP_TRAIN_CTL);
>  		if (!(val & PHB_PCIE_DLP_DL_PGRESET))
>  			break;
>  		time_wait_ms(1);
> @@ -4318,40 +4318,40 @@ static void phb4_init_hw(struct phb4 *p, bool first_init)
>  	 */
>  
>  	/* Init_2 - Mask FIRs */
> -	out_be64(p->regs + PHB_LEM_ERROR_MASK,			0xffffffffffffffffull);
> +	phb4_write_reg(p, PHB_LEM_ERROR_MASK,			0xffffffffffffffffull);
>  
>  	/* Init_3 - TCE tag enable */
> -	out_be64(p->regs + PHB_TCE_TAG_ENABLE,			0xffffffffffffffffull);
> +	phb4_write_reg(p, PHB_TCE_TAG_ENABLE,			0xffffffffffffffffull);
>  
>  	/* Init_4 - PCIE System Configuration Register
>  	 *
>  	 * Adjust max speed based on system config
>  	 */
> -	val = in_be64(p->regs + PHB_PCIE_SCR);
> +	val = phb4_read_reg(p, PHB_PCIE_SCR);
>  	PHBDBG(p, "Default system config: 0x%016llx\n", val);
>  	val = SETFIELD(PHB_PCIE_SCR_MAXLINKSPEED, val, p->max_link_speed);
> -	out_be64(p->regs + PHB_PCIE_SCR, val);
> +	phb4_write_reg(p, PHB_PCIE_SCR, val);
>  	PHBDBG(p, "New system config    : 0x%016llx\n",
> -	       in_be64(p->regs + PHB_PCIE_SCR));
> +	       phb4_read_reg(p, PHB_PCIE_SCR));
>  
>  	/* Init_5 - deassert CFG reset */
> -	creset = in_be64(p->regs + PHB_PCIE_CRESET);
> +	creset = phb4_read_reg(p, PHB_PCIE_CRESET);
>  	PHBDBG(p, "Initial PHB CRESET is 0x%016llx\n", creset);
>  	creset &= ~PHB_PCIE_CRESET_CFG_CORE;
> -	out_be64(p->regs + PHB_PCIE_CRESET,			creset);
> +	phb4_write_reg(p, PHB_PCIE_CRESET,			creset);
>  
>  	/* Init_6..13 - PCIE DLP Lane EQ control */
>  	if (p->lane_eq) {
> -		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL0, be64_to_cpu(p->lane_eq[0]));
> -		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL1, be64_to_cpu(p->lane_eq[1]));
> -		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL2, be64_to_cpu(p->lane_eq[2]));
> -		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL3, be64_to_cpu(p->lane_eq[3]));
> -		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL20, be64_to_cpu(p->lane_eq[4]));
> -		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL21, be64_to_cpu(p->lane_eq[5]));
> +		phb4_write_reg(p, PHB_PCIE_LANE_EQ_CNTL0, be64_to_cpu(p->lane_eq[0]));
> +		phb4_write_reg(p, PHB_PCIE_LANE_EQ_CNTL1, be64_to_cpu(p->lane_eq[1]));
> +		phb4_write_reg(p, PHB_PCIE_LANE_EQ_CNTL2, be64_to_cpu(p->lane_eq[2]));
> +		phb4_write_reg(p, PHB_PCIE_LANE_EQ_CNTL3, be64_to_cpu(p->lane_eq[3]));
> +		phb4_write_reg(p, PHB_PCIE_LANE_EQ_CNTL20, be64_to_cpu(p->lane_eq[4]));
> +		phb4_write_reg(p, PHB_PCIE_LANE_EQ_CNTL21, be64_to_cpu(p->lane_eq[5]));
>  		if (p->rev == PHB4_REV_NIMBUS_DD10) {
> -			out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL22,
> +			phb4_write_reg(p, PHB_PCIE_LANE_EQ_CNTL22,
>  				 be64_to_cpu(p->lane_eq[6]));
> -			out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL23,
> +			phb4_write_reg(p, PHB_PCIE_LANE_EQ_CNTL23,
>  				 be64_to_cpu(p->lane_eq[7]));
>  		}
>  	}
> @@ -4367,7 +4367,7 @@ static void phb4_init_hw(struct phb4 *p, bool first_init)
>  	 */
>  	creset &= ~(PHB_PCIE_CRESET_TLDLP | PHB_PCIE_CRESET_PBL);
>  	creset |= PHB_PCIE_CRESET_PIPE_N;
> -	out_be64(p->regs + PHB_PCIE_CRESET,			   creset);
> +	phb4_write_reg(p, PHB_PCIE_CRESET,			   creset);
>  
>  	/* Init_16 - Wait for DLP PGRESET to clear */
>  	if (!phb4_wait_dlp_reset(p))
> @@ -4385,16 +4385,16 @@ static void phb4_init_hw(struct phb4 *p, bool first_init)
>  	if (!pci_eeh_mmio)
>  		val |= PHB_CTRLR_MMIO_EEH_DISABLE;
>  
> -	out_be64(p->regs + PHB_CTRLR, val);
> +	phb4_write_reg(p, PHB_CTRLR, val);
>  
>  	/* Init_18..41 - Architected IODA3 inits */
>  	phb4_init_ioda3(p);
>  
>  	/* Init_42..45 - Clear DLP error logs */
> -	out_be64(p->regs + 0x1aa0,			0xffffffffffffffffull);
> -	out_be64(p->regs + 0x1aa8,			0xffffffffffffffffull);
> -	out_be64(p->regs + 0x1ab0,			0xffffffffffffffffull);
> -	out_be64(p->regs + 0x1ab8,			0x0);
> +	phb4_write_reg(p, 0x1aa0,			0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x1aa8,			0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x1ab0,			0xffffffffffffffffull);
> +	phb4_write_reg(p, 0x1ab8,			0x0);
>  
>  
>  	/* Init_46..54 : Init root complex config space */
> @@ -4432,30 +4432,30 @@ static void phb4_init_hw(struct phb4 *p, bool first_init)
>  			    PCI_CFG_STAT_RECV_PERR);
>  
>  	/* Init_126..130 - Re-enable error interrupts */
> -	out_be64(p->regs + PHB_ERR_IRQ_ENABLE,			0xca8880cc00000000ull);
> -	out_be64(p->regs + PHB_TXE_ERR_IRQ_ENABLE,		0x2008400e08200000ull);
> -	out_be64(p->regs + PHB_RXE_ARB_ERR_IRQ_ENABLE,		0xc40028fc01804070ull);
> -	out_be64(p->regs + PHB_RXE_MRG_ERR_IRQ_ENABLE,		0x00006100008000a8ull);
> +	phb4_write_reg(p, PHB_ERR_IRQ_ENABLE,			0xca8880cc00000000ull);
> +	phb4_write_reg(p, PHB_TXE_ERR_IRQ_ENABLE,		0x2008400e08200000ull);
> +	phb4_write_reg(p, PHB_RXE_ARB_ERR_IRQ_ENABLE,		0xc40028fc01804070ull);
> +	phb4_write_reg(p, PHB_RXE_MRG_ERR_IRQ_ENABLE,		0x00006100008000a8ull);
>  	if (p->rev == PHB4_REV_NIMBUS_DD10)
> -		out_be64(p->regs + PHB_RXE_TCE_ERR_IRQ_ENABLE,	0x6051005000000000ull);
> +		phb4_write_reg(p, PHB_RXE_TCE_ERR_IRQ_ENABLE,	0x6051005000000000ull);
>  	else
> -		out_be64(p->regs + PHB_RXE_TCE_ERR_IRQ_ENABLE,	0x60510050c0000000ull);
> +		phb4_write_reg(p, PHB_RXE_TCE_ERR_IRQ_ENABLE,	0x60510050c0000000ull);
>  
>  	/* Init_131 - Re-enable LEM error mask */
> -	out_be64(p->regs + PHB_LEM_ERROR_MASK,			0x0000000000000000ull);
> +	phb4_write_reg(p, PHB_LEM_ERROR_MASK,			0x0000000000000000ull);
>  
>  
>  	/* Init_132 - Enable DMA address speculation */
> -	out_be64(p->regs + PHB_TCE_SPEC_CTL,			0x0000000000000000ull);
> +	phb4_write_reg(p, PHB_TCE_SPEC_CTL,			0x0000000000000000ull);
>  
>  	/* Init_133 - Timeout Control Register 1 */
> -	out_be64(p->regs + PHB_TIMEOUT_CTRL1,			0x0018150000200000ull);
> +	phb4_write_reg(p, PHB_TIMEOUT_CTRL1,			0x0018150000200000ull);
>  
>  	/* Init_134 - Timeout Control Register 2 */
> -	out_be64(p->regs + PHB_TIMEOUT_CTRL2,			0x0000181700000000ull);
> +	phb4_write_reg(p, PHB_TIMEOUT_CTRL2,			0x0000181700000000ull);
>  
>  	/* Init_135 - PBL Timeout Control Register */
> -	out_be64(p->regs + PHB_PBL_TIMEOUT_CTRL,		0x2015000000000000ull);
> +	phb4_write_reg(p, PHB_PBL_TIMEOUT_CTRL,		0x2015000000000000ull);
>  
>  	/* Mark the PHB as functional which enables all the various sequences */
>  	p->state = PHB4_STATE_FUNCTIONAL;
> @@ -4487,7 +4487,7 @@ static bool phb4_read_capabilities(struct phb4 *p)
>  	PHBDBG(p, "Core revision 0x%x\n", p->rev);
>  
>  	/* Read EEH capabilities */
> -	val = in_be64(p->regs + PHB_PHB4_EEH_CAP);
> +	val = phb4_read_reg(p, PHB_PHB4_EEH_CAP);
>  	if (val == 0xffffffffffffffff) {
>  		PHBERR(p, "Failed to read EEH cap, PHB appears broken\n");
>  		return false;
> @@ -4506,7 +4506,7 @@ static bool phb4_read_capabilities(struct phb4 *p)
>  	if (p->rev >= PHB4_REV_NIMBUS_DD20)
>  		p->tvt_size *= 2;
>  
> -	val = in_be64(p->regs + PHB_PHB4_IRQ_CAP);
> +	val = phb4_read_reg(p, PHB_PHB4_IRQ_CAP);
>  	if (val == 0xffffffffffffffff) {
>  		PHBERR(p, "Failed to read IRQ cap, PHB appears broken\n");
>  		return false;
> @@ -4759,9 +4759,9 @@ static int64_t phb4_ndd1_lsi_set_xive(struct irq_source *is, uint32_t isn,
>  	 * will go away soon enough.
>  	 */
>  	if (priority == 0xff)
> -		out_be64(p->regs + PHB_IODA_DATA0, IODA3_LIST_Q);
> +		phb4_write_reg(p, PHB_IODA_DATA0, IODA3_LIST_Q);
>  	else {
> -		out_be64(p->regs + PHB_IODA_DATA0, IODA3_LIST_P);
> +		phb4_write_reg(p, PHB_IODA_DATA0, IODA3_LIST_P);
>  		__irq_source_eoi(is, isn);
>  	}
>
Guilherme G. Piccoli Oct. 3, 2017, 2:01 p.m. | #3
On 10/03/2017 10:49 AM, Benjamin Herrenschmidt wrote:
> On Mon, 2017-10-02 at 19:23 -0300, Guilherme G. Piccoli wrote:
>> Currently, the PHB registers access is mix-performed by the read/write
>> primitives or the open coded in/out procedures.
>>
>> This patch change all open coded in/outs to use the read/write primitives.
>> No functional change is expected.
> 
> It adds overhead for registers that are never going to be used via
> XSCOM in practice (what would be the point ?)
> 
> If you get fenced during some of those init procedures you are pretty
> much a goner already. This looks like plaster on a wooden leg to me. 
> 
> Care to explain more what you are trying to achieve, it's not clear...
> 

Patch 1 was more a code clean-up, but since it's adding overhead, let's
drop the entire series! Thanks a lot for the review!

Patch

diff --git a/hw/phb4.c b/hw/phb4.c
index b94d4925..99902d3a 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -480,7 +480,7 @@  static int64_t phb4_pcicfg_read(struct phb4 *p, uint32_t bdfn,
 			return OPAL_PARAMETER;
 		}
 	} else {
-		out_be64(p->regs + PHB_CONFIG_ADDRESS, addr);
+		phb4_write_reg(p, PHB_CONFIG_ADDRESS, addr);
 		switch(size) {
 		case 1:
 			*((uint8_t *)data) =
@@ -559,7 +559,7 @@  static int64_t phb4_pcicfg_write(struct phb4 *p, uint32_t bdfn,
 		/* We don't support ASB config space writes */
 		return OPAL_UNSUPPORTED;
 	} else {
-		out_be64(p->regs + PHB_CONFIG_ADDRESS, addr);
+		phb4_write_reg(p, PHB_CONFIG_ADDRESS, addr);
 		switch(size) {
 		case 1:
 			out_8(p->regs + PHB_CONFIG_DATA + (offset & 3), data);
@@ -977,7 +977,7 @@  static int64_t phb4_wait_bit(struct phb4 *p, uint32_t reg,
 		return OPAL_SUCCESS;
 
 	for (;;) {
-		val = in_be64(p->regs + reg);
+		val = phb4_read_reg(p, reg);
 		if (val == 0xffffffffffffffffull) {
 			/* XXX Fenced ? */
 			return OPAL_HARDWARE;
@@ -1035,7 +1035,7 @@  static int64_t phb4_tce_kill(struct phb *phb, uint32_t kill_type,
 				return OPAL_PARAMETER;
 			}
 			/* Perform kill */
-			out_be64(p->regs + PHB_TCE_KILL, PHB_TCE_KILL_ONE | val);
+			phb4_write_reg(p, PHB_TCE_KILL, PHB_TCE_KILL_ONE | val);
 			/* Next page */
 			dma_addr += tce_size;
 		}
@@ -1049,7 +1049,7 @@  static int64_t phb4_tce_kill(struct phb *phb, uint32_t kill_type,
 		if (rc)
 			return rc;
 		/* Perform kill */
-		out_be64(p->regs + PHB_TCE_KILL, PHB_TCE_KILL_PE |
+		phb4_write_reg(p, PHB_TCE_KILL, PHB_TCE_KILL_PE |
 			 SETFIELD(PHB_TCE_KILL_PENUM, 0ull, pe_number));
 		break;
 	case OPAL_PCI_TCE_KILL_ALL:
@@ -1061,14 +1061,14 @@  static int64_t phb4_tce_kill(struct phb *phb, uint32_t kill_type,
 		if (rc)
 			return rc;
 		/* Perform kill */
-		out_be64(p->regs + PHB_TCE_KILL, PHB_TCE_KILL_ALL);
+		phb4_write_reg(p, PHB_TCE_KILL, PHB_TCE_KILL_ALL);
 		break;
 	default:
 		return OPAL_PARAMETER;
 	}
 
 	/* Start DMA sync process */
-	out_be64(p->regs + PHB_DMARD_SYNC, PHB_DMARD_SYNC_START);
+	phb4_write_reg(p, PHB_DMARD_SYNC, PHB_DMARD_SYNC_START);
 
 	/* Wait for kill to complete */
 	rc = phb4_wait_bit(p, PHB_Q_DMA_R, PHB_Q_DMA_R_TCE_KILL_STATUS, 0);
@@ -1104,37 +1104,37 @@  static int64_t phb4_ioda_reset(struct phb *phb, bool purge)
 
 	/* Init_30..31 - Errata workaround, clear PESTA entry 0 */
 	phb4_ioda_sel(p, IODA3_TBL_PESTA, 0, false);
-	out_be64(p->regs + PHB_IODA_DATA0, 0);
+	phb4_write_reg(p, PHB_IODA_DATA0, 0);
 
 	/* Init_32..33 - MIST  */
 	phb4_ioda_sel(p, IODA3_TBL_MIST, 0, true);
-	val = in_be64(p->regs + PHB_IODA_ADDR);
+	val = phb4_read_reg(p, PHB_IODA_ADDR);
 	val = SETFIELD(PHB_IODA_AD_MIST_PWV, val, 0xf);
-	out_be64(p->regs + PHB_IODA_ADDR, val);
+	phb4_write_reg(p, PHB_IODA_ADDR, val);
 	for (i = 0; i < (p->num_irqs/4); i++)
-		out_be64(p->regs + PHB_IODA_DATA0, p->mist_cache[i]);
+		phb4_write_reg(p, PHB_IODA_DATA0, p->mist_cache[i]);
 
 	/* Init_34..35 - MRT */
 	phb4_ioda_sel(p, IODA3_TBL_MRT, 0, true);
 	for (i = 0; i < p->mrt_size; i++)
-		out_be64(p->regs + PHB_IODA_DATA0, 0);
+		phb4_write_reg(p, PHB_IODA_DATA0, 0);
 
 	/* Init_36..37 - TVT */
 	phb4_ioda_sel(p, IODA3_TBL_TVT, 0, true);
 	for (i = 0; i < p->tvt_size; i++)
-		out_be64(p->regs + PHB_IODA_DATA0, p->tve_cache[i]);
+		phb4_write_reg(p, PHB_IODA_DATA0, p->tve_cache[i]);
 
 	/* Init_38..39 - MBT */
 	phb4_ioda_sel(p, IODA3_TBL_MBT, 0, true);
 	for (i = 0; i < p->mbt_size; i++) {
-		out_be64(p->regs + PHB_IODA_DATA0, p->mbt_cache[i][0]);
-		out_be64(p->regs + PHB_IODA_DATA0, p->mbt_cache[i][1]);
+		phb4_write_reg(p, PHB_IODA_DATA0, p->mbt_cache[i][0]);
+		phb4_write_reg(p, PHB_IODA_DATA0, p->mbt_cache[i][1]);
 	}
 
 	/* Init_40..41 - MDT */
 	phb4_ioda_sel(p, IODA3_TBL_MDT, 0, true);
 	for (i = 0; i < p->max_num_pes; i++)
-		out_be64(p->regs + PHB_IODA_DATA0, p->mdt_cache[i]);
+		phb4_write_reg(p, PHB_IODA_DATA0, p->mdt_cache[i]);
 
 	/* Additional OPAL specific inits */
 
@@ -1147,17 +1147,17 @@  static int64_t phb4_ioda_reset(struct phb *phb, bool purge)
 	/* Clear PEST & PEEV */
 	for (i = 0; i < p->max_num_pes; i++) {
 		phb4_ioda_sel(p, IODA3_TBL_PESTA, i, false);
-		out_be64(p->regs + PHB_IODA_DATA0, 0);
+		phb4_write_reg(p, PHB_IODA_DATA0, 0);
 		phb4_ioda_sel(p, IODA3_TBL_PESTB, i, false);
-		out_be64(p->regs + PHB_IODA_DATA0, 0);
+		phb4_write_reg(p, PHB_IODA_DATA0, 0);
 	}
 
 	phb4_ioda_sel(p, IODA3_TBL_PEEV, 0, true);
 	for (i = 0; i < p->max_num_pes/64; i++)
-		out_be64(p->regs + PHB_IODA_DATA0, 0);
+		phb4_write_reg(p, PHB_IODA_DATA0, 0);
 
 	/* Invalidate RTE, TCE cache */
-	out_be64(p->regs + PHB_RTC_INVALIDATE, PHB_RTC_INVALIDATE_ALL);
+	phb4_write_reg(p, PHB_RTC_INVALIDATE, PHB_RTC_INVALIDATE_ALL);
 
 	return phb4_tce_kill(&p->phb, OPAL_PCI_TCE_KILL_ALL, 0, 0, 0, 0);
 }
@@ -1173,9 +1173,9 @@  static int64_t phb4_papr_errinjct_reset(struct phb *phb)
 {
 	struct phb4 *p = phb_to_phb4(phb);
 
-	out_be64(p->regs + PHB_PAPR_ERR_INJ_CTL, 0x0ul);
-	out_be64(p->regs + PHB_PAPR_ERR_INJ_ADDR, 0x0ul);
-	out_be64(p->regs + PHB_PAPR_ERR_INJ_MASK, 0x0ul);
+	phb4_write_reg(p, PHB_PAPR_ERR_INJ_CTL, 0x0ul);
+	phb4_write_reg(p, PHB_PAPR_ERR_INJ_ADDR, 0x0ul);
+	phb4_write_reg(p, PHB_PAPR_ERR_INJ_MASK, 0x0ul);
 
 	return OPAL_SUCCESS;
 }
@@ -1353,8 +1353,8 @@  static int64_t phb4_phb_mmio_enable(struct phb __unused *phb,
 	p->mbt_cache[window_num][0] = mbt0;
 	p->mbt_cache[window_num][1] = mbt1;
 	phb4_ioda_sel(p, IODA3_TBL_MBT, window_num << 1, true);
-	out_be64(p->regs + PHB_IODA_DATA0, mbt0);
-	out_be64(p->regs + PHB_IODA_DATA0, mbt1);
+	phb4_write_reg(p, PHB_IODA_DATA0, mbt0);
+	phb4_write_reg(p, PHB_IODA_DATA0, mbt1);
 
 	return OPAL_SUCCESS;
 }
@@ -1404,13 +1404,13 @@  static int64_t phb4_map_pe_mmio_window(struct phb *phb,
 			p->mdt_cache[segment_num << 1] = mdt0;
 			p->mdt_cache[(segment_num << 1) + 1] = mdt1;
 			phb4_ioda_sel(p, IODA3_TBL_MDT, segment_num << 1, true);
-			out_be64(p->regs + PHB_IODA_DATA0, mdt0);
-			out_be64(p->regs + PHB_IODA_DATA0, mdt1);
+			phb4_write_reg(p, PHB_IODA_DATA0, mdt0);
+			phb4_write_reg(p, PHB_IODA_DATA0, mdt1);
 		} else {
 			mdt0 = p->mdt_cache[segment_num];
 			mdt0 = SETFIELD(IODA3_MDT_PE_A, mdt0, pe_number);
 			phb4_ioda_sel(p, IODA3_TBL_MDT, segment_num, false);
-			out_be64(p->regs + PHB_IODA_DATA0, mdt0);
+			phb4_write_reg(p, PHB_IODA_DATA0, mdt0);
 		}
 		break;
 	case OPAL_M64_WINDOW_TYPE:
@@ -1471,7 +1471,7 @@  static int64_t phb4_map_pe_dma_window(struct phb *phb,
 	 */
 	if (tce_table_size == 0) {
 		phb4_ioda_sel(p, IODA3_TBL_TVT, window_id, false);
-		out_be64(p->regs + PHB_IODA_DATA0, 0);
+		phb4_write_reg(p, PHB_IODA_DATA0, 0);
 		p->tve_cache[window_id] = 0;
 		return OPAL_SUCCESS;
 	}
@@ -1511,7 +1511,7 @@  static int64_t phb4_map_pe_dma_window(struct phb *phb,
 	data64 = SETFIELD(IODA3_TVT_NUM_LEVELS, data64, tce_levels - 1);
 
 	phb4_ioda_sel(p, IODA3_TBL_TVT, window_id, false);
-	out_be64(p->regs + PHB_IODA_DATA0, data64);
+	phb4_write_reg(p, PHB_IODA_DATA0, data64);
 	p->tve_cache[window_id] = data64;
 
 	return OPAL_SUCCESS;
@@ -1574,7 +1574,7 @@  static int64_t phb4_map_pe_dma_window_real(struct phb *phb,
 	}
 
 	phb4_ioda_sel(p, IODA3_TBL_TVT, window_id, false);
-	out_be64(p->regs + PHB_IODA_DATA0, tve);
+	phb4_write_reg(p, PHB_IODA_DATA0, tve);
 	p->tve_cache[window_id] = tve;
 
 	return OPAL_SUCCESS;
@@ -1608,12 +1608,12 @@  static int64_t phb4_set_ive_pe(struct phb *phb,
 	/* We need to inject the appropriate MIST write enable bit
 	 * in the IODA table address register
 	 */
-	val = in_be64(p->regs + PHB_IODA_ADDR);
+	val = phb4_read_reg(p, PHB_IODA_ADDR);
 	val = SETFIELD(PHB_IODA_AD_MIST_PWV, val, 8 >> mist_quad);
-	out_be64(p->regs + PHB_IODA_ADDR, val);
+	phb4_write_reg(p, PHB_IODA_ADDR, val);
 
 	/* Write entry */
-	out_be64(p->regs + PHB_IODA_DATA0, p->mist_cache[mist_idx]);
+	phb4_write_reg(p, PHB_IODA_DATA0, p->mist_cache[mist_idx]);
 
 	return OPAL_SUCCESS;
 }
@@ -2074,7 +2074,7 @@  static int64_t phb4_set_pe(struct phb *phb,
 	}
 
 	/* Invalidate the entire RTC */
-	out_be64(p->regs + PHB_RTC_INVALIDATE, PHB_RTC_INVALIDATE_ALL);
+	phb4_write_reg(p, PHB_RTC_INVALIDATE, PHB_RTC_INVALIDATE_ALL);
 
 	return OPAL_SUCCESS;
 }
@@ -2135,15 +2135,15 @@  static void phb4_prepare_link_change(struct pci_slot *slot, bool is_up)
 		p->flags &= ~PHB4_CFG_BLOCKED;
 
 		/* Re-enable link down errors */
-		out_be64(p->regs + PHB_PCIE_MISC_STRAP,
+		phb4_write_reg(p, PHB_PCIE_MISC_STRAP,
 			 0x0000060000000000ull);
 
 		/* Re-enable error status indicators that trigger irqs */
-		out_be64(p->regs + PHB_REGB_ERR_INF_ENABLE,
+		phb4_write_reg(p, PHB_REGB_ERR_INF_ENABLE,
 			 0x2130006efca8bc00ull);
-		out_be64(p->regs + PHB_REGB_ERR_ERC_ENABLE,
+		phb4_write_reg(p, PHB_REGB_ERR_ERC_ENABLE,
 			 0x0000000000000000ull);
-		out_be64(p->regs + PHB_REGB_ERR_FAT_ENABLE,
+		phb4_write_reg(p, PHB_REGB_ERR_FAT_ENABLE,
 			 0xde8fff91035743ffull);
 
 		/*
@@ -2167,12 +2167,12 @@  static void phb4_prepare_link_change(struct pci_slot *slot, bool is_up)
 				    PCIECAP_AER_CE_MASK, reg32);
 
 		/* Clear error link enable & error link down kill enable */
-		out_be64(p->regs + PHB_PCIE_MISC_STRAP, 0);
+		phb4_write_reg(p, PHB_PCIE_MISC_STRAP, 0);
 
 		/* Disable all error status indicators that trigger irqs */
-		out_be64(p->regs + PHB_REGB_ERR_INF_ENABLE, 0);
-		out_be64(p->regs + PHB_REGB_ERR_ERC_ENABLE, 0);
-		out_be64(p->regs + PHB_REGB_ERR_FAT_ENABLE, 0);
+		phb4_write_reg(p, PHB_REGB_ERR_INF_ENABLE, 0);
+		phb4_write_reg(p, PHB_REGB_ERR_ERC_ENABLE, 0);
+		phb4_write_reg(p, PHB_REGB_ERR_FAT_ENABLE, 0);
 
 		/* Block PCI-CFG access */
 		p->flags |= PHB4_CFG_BLOCKED;
@@ -2189,7 +2189,7 @@  static int64_t phb4_get_presence_state(struct pci_slot *slot, uint8_t *val)
 		return OPAL_HARDWARE;
 
 	/* Check hotplug status */
-	hps = in_be64(p->regs + PHB_PCIE_HOTPLUG_STATUS);
+	hps = phb4_read_reg(p, PHB_PCIE_HOTPLUG_STATUS);
 	if (!(hps & PHB_PCIE_HPSTAT_PRESENCE)) {
 		*val = OPAL_PCI_SLOT_PRESENT;
 	} else {
@@ -2198,7 +2198,7 @@  static int64_t phb4_get_presence_state(struct pci_slot *slot, uint8_t *val)
 		 * we are on a broken simulation environment and still
 		 * return a valid presence. Otherwise, not present.
 		 */
-		dtctl = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
+		dtctl = phb4_read_reg(p, PHB_PCIE_DLP_TRAIN_CTL);
 		if (dtctl & PHB_PCIE_DLP_TL_LINKACT) {
 			PHBERR(p, "Presence detect 0 but link set !\n");
 			*val = OPAL_PCI_SLOT_PRESENT;
@@ -2220,7 +2220,7 @@  static int64_t phb4_get_link_info(struct pci_slot *slot, uint8_t *speed,
 	uint8_t s;
 
 	/* Link is up, let's find the actual speed */
-	reg = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
+	reg = phb4_read_reg(p, PHB_PCIE_DLP_TRAIN_CTL);
 	if (!(reg & PHB_PCIE_DLP_TL_LINKACT)) {
 		*width = 0;
 		if (speed)
@@ -2350,7 +2350,7 @@  static bool phb4_fenced(struct phb4 *p)
 	 * An all 1's from the PHB indicates a PHB freeze/fence. We
 	 * don't really differenciate them at this point.
 	 */
-	if (in_be64(p->regs + PHB_CPU_LOADSTORE_STATUS)!= 0xfffffffffffffffful)
+	if (phb4_read_reg(p, PHB_CPU_LOADSTORE_STATUS)!= 0xfffffffffffffffful)
 		return false;
 
 	PHBERR(p, "PHB Freeze/Fence detected !\n");
@@ -2529,7 +2529,7 @@  static void phb4_training_trace(struct phb4 *p)
 
 	while(1) {
 		now = mftb();
-		reg = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
+		reg = phb4_read_reg(p, PHB_PCIE_DLP_TRAIN_CTL);
 		if (reg != reglast)
 			phb4_train_info(p, reg, now - start);
 		reglast = reg;
@@ -2573,7 +2573,7 @@  static int64_t phb4_poll_link(struct pci_slot *slot)
 		 * because simics doesn't seem to implement the electrical
 		 * link bit at all
 		 */
-		reg = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
+		reg = phb4_read_reg(p, PHB_PCIE_DLP_TRAIN_CTL);
 		if (!phb4_check_reg(p, reg)) {
 			PHBERR(p, "PHB fence waiting for electrical link\n");
 			return phb4_retry_state(slot);
@@ -2596,7 +2596,7 @@  static int64_t phb4_poll_link(struct pci_slot *slot)
 		/* Retry */
 		return pci_slot_set_sm_timeout(slot, msecs_to_tb(10));
 	case PHB4_SLOT_LINK_WAIT:
-		reg = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
+		reg = phb4_read_reg(p, PHB_PCIE_DLP_TRAIN_CTL);
 		if (!phb4_check_reg(p, reg)) {
 			PHBERR(p, "LINK: PHB fence waiting for link training\n");
 			return phb4_retry_state(slot);
@@ -2621,7 +2621,7 @@  static int64_t phb4_poll_link(struct pci_slot *slot)
 			PHBERR(p, "LINK: PHB fenced waiting for stabilty\n");
 			return phb4_retry_state(slot);
 		}
-		reg = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
+		reg = phb4_read_reg(p, PHB_PCIE_DLP_TRAIN_CTL);
 		if (!phb4_check_reg(p, reg)) {
 			PHBERR(p, "LINK: PHB fence reading training control\n");
 			return phb4_retry_state(slot);
@@ -2736,9 +2736,9 @@  static int64_t phb4_freset(struct pci_slot *slot)
 	case PHB4_SLOT_FRESET_START:
 		if (!p->skip_perst) {
 			PHBDBG(p, "FRESET: Assert\n");
-			reg = in_be64(p->regs + PHB_PCIE_CRESET);
+			reg = phb4_read_reg(p, PHB_PCIE_CRESET);
 			reg &= ~PHB_PCIE_CRESET_PERST_N;
-			out_be64(p->regs + PHB_PCIE_CRESET, reg);
+			phb4_write_reg(p, PHB_PCIE_CRESET, reg);
 			pci_slot_set_state(slot,
 				PHB4_SLOT_FRESET_ASSERT_DELAY);
 			/* 250ms assert time aligns with powernv */
@@ -2756,15 +2756,15 @@  static int64_t phb4_freset(struct pci_slot *slot)
 
 		if (pci_tracing) {
 			/* Enable tracing */
-			reg = in_be64(p->regs + PHB_PCIE_DLP_TRWCTL);
-			out_be64(p->regs + PHB_PCIE_DLP_TRWCTL,
+			reg = phb4_read_reg(p, PHB_PCIE_DLP_TRWCTL);
+			phb4_write_reg(p, PHB_PCIE_DLP_TRWCTL,
 				 reg | PHB_PCIE_DLP_TRWCTL_EN);
 		}
 
 		PHBDBG(p, "FRESET: Deassert\n");
-		reg = in_be64(p->regs + PHB_PCIE_CRESET);
+		reg = phb4_read_reg(p, PHB_PCIE_CRESET);
 		reg |= PHB_PCIE_CRESET_PERST_N;
-		out_be64(p->regs + PHB_PCIE_CRESET, reg);
+		phb4_write_reg(p, PHB_PCIE_CRESET, reg);
 		pci_slot_set_state(slot,
 			PHB4_SLOT_FRESET_DEASSERT_DELAY);
 
@@ -3002,7 +3002,7 @@  static int64_t phb4_eeh_freeze_status(struct phb *phb, uint64_t pe_number,
 
 	/* Check the PEEV */
 	phb4_ioda_sel(p, IODA3_TBL_PEEV, pe_number / 64, false);
-	peev = in_be64(p->regs + PHB_IODA_DATA0);
+	peev = phb4_read_reg(p, PHB_IODA_DATA0);
 	if (!(peev & peev_bit))
 		return OPAL_SUCCESS;
 
@@ -3013,9 +3013,9 @@  static int64_t phb4_eeh_freeze_status(struct phb *phb, uint64_t pe_number,
 
 	/* Read the PESTA & PESTB */
 	phb4_ioda_sel(p, IODA3_TBL_PESTA, pe_number, false);
-	pesta = in_be64(p->regs + PHB_IODA_DATA0);
+	pesta = phb4_read_reg(p, PHB_IODA_DATA0);
 	phb4_ioda_sel(p, IODA3_TBL_PESTB, pe_number, false);
-	pestb = in_be64(p->regs + PHB_IODA_DATA0);
+	pestb = phb4_read_reg(p, PHB_IODA_DATA0);
 
 	/* Convert them */
 	if (pesta & IODA3_PESTA_MMIO_FROZEN)
@@ -3045,7 +3045,7 @@  static int64_t phb4_eeh_freeze_clear(struct phb *phb, uint64_t pe_number,
 	 * contain a freeze state from a previous error or simply set
 	 * explicitely by the user
 	 */
-	err = in_be64(p->regs + PHB_ETU_ERR_SUMMARY);
+	err = phb4_read_reg(p, PHB_ETU_ERR_SUMMARY);
 	if (err == 0xffffffffffffffff) {
 		if (phb4_fenced(p)) {
 			PHBERR(p, "eeh_freeze_clear on fenced PHB\n");
@@ -3061,18 +3061,18 @@  static int64_t phb4_eeh_freeze_clear(struct phb *phb, uint64_t pe_number,
 	 */
 	if (eeh_action_token & OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO) {
 		phb4_ioda_sel(p, IODA3_TBL_PESTA, pe_number, false);
-		out_be64(p->regs + PHB_IODA_DATA0, 0);
+		phb4_write_reg(p, PHB_IODA_DATA0, 0);
 	}
 	if (eeh_action_token & OPAL_EEH_ACTION_CLEAR_FREEZE_DMA) {
 		phb4_ioda_sel(p, IODA3_TBL_PESTB, pe_number, false);
-		out_be64(p->regs + PHB_IODA_DATA0, 0);
+		phb4_write_reg(p, PHB_IODA_DATA0, 0);
 	}
 
 
 	/* Update ER pending indication */
 	phb4_ioda_sel(p, IODA3_TBL_PEEV, 0, true);
 	for (i = 0; i < p->num_pes/64; i++) {
-		peev = in_be64(p->regs + PHB_IODA_DATA0);
+		peev = phb4_read_reg(p, PHB_IODA_DATA0);
 		if (peev) {
 			frozen_pe = true;
 			break;
@@ -3108,16 +3108,16 @@  static int64_t phb4_eeh_freeze_set(struct phb *phb, uint64_t pe_number,
 
 	if (eeh_action_token & OPAL_EEH_ACTION_SET_FREEZE_MMIO) {
 		phb4_ioda_sel(p, IODA3_TBL_PESTA, pe_number, false);
-		data = in_be64(p->regs + PHB_IODA_DATA0);
+		data = phb4_read_reg(p, PHB_IODA_DATA0);
 		data |= IODA3_PESTA_MMIO_FROZEN;
-		out_be64(p->regs + PHB_IODA_DATA0, data);
+		phb4_write_reg(p, PHB_IODA_DATA0, data);
 	}
 
 	if (eeh_action_token & OPAL_EEH_ACTION_SET_FREEZE_DMA) {
 		phb4_ioda_sel(p, IODA3_TBL_PESTB, pe_number, false);
-		data = in_be64(p->regs + PHB_IODA_DATA0);
+		data = phb4_read_reg(p, PHB_IODA_DATA0);
 		data |= IODA3_PESTB_DMA_STOPPED;
-		out_be64(p->regs + PHB_IODA_DATA0, data);
+		phb4_write_reg(p, PHB_IODA_DATA0, data);
 	}
 
 	return OPAL_SUCCESS;
@@ -3165,7 +3165,7 @@  static int64_t phb4_eeh_next_error(struct phb *phb,
 	if (!phb4_err_pending(p)) {
 		phb4_ioda_sel(p, IODA3_TBL_PEEV, 0, true);
 		for (i = 0; i < peev_size; i++) {
-			peev = in_be64(p->regs + PHB_IODA_DATA0);
+			peev = phb4_read_reg(p, PHB_IODA_DATA0);
 			if (peev) {
 				p->err.err_src	 = PHB4_ERR_SRC_PHB;
 				p->err.err_class = PHB4_ERR_CLASS_ER;
@@ -3211,7 +3211,7 @@  static int64_t phb4_eeh_next_error(struct phb *phb,
 
 			for (i = peev_size - 1; i >= 0; i--) {
 				phb4_ioda_sel(p, IODA3_TBL_PEEV, i, false);
-				peev = in_be64(p->regs + PHB_IODA_DATA0);
+				peev = phb4_read_reg(p, PHB_IODA_DATA0);
 				for (j = 0; j < 64; j++) {
 					if (peev & PPC_BIT(j)) {
 						*first_frozen_pe = i * 64 + j;
@@ -3254,9 +3254,9 @@  static int64_t phb4_err_inject_finalize(struct phb4 *phb, uint64_t addr,
 	else
 		ctrl |= PHB_PAPR_ERR_INJ_CTL_RD;
 
-	out_be64(phb->regs + PHB_PAPR_ERR_INJ_ADDR, addr);
-	out_be64(phb->regs + PHB_PAPR_ERR_INJ_MASK, mask);
-	out_be64(phb->regs + PHB_PAPR_ERR_INJ_CTL, ctrl);
+	phb4_write_reg(phb, PHB_PAPR_ERR_INJ_ADDR,	addr);
+	phb4_write_reg(phb, PHB_PAPR_ERR_INJ_MASK,	mask);
+	phb4_write_reg(phb, PHB_PAPR_ERR_INJ_CTL,	ctrl);
 
 	return OPAL_SUCCESS;
 }
@@ -3376,7 +3376,7 @@  static int64_t phb4_err_inject(struct phb *phb, uint64_t pe_number,
 		return OPAL_PARAMETER;
 
 	/* Clear leftover from last time */
-	out_be64(p->regs + PHB_PAPR_ERR_INJ_CTL, 0x0ul);
+	phb4_write_reg(p, PHB_PAPR_ERR_INJ_CTL, 0x0ul);
 
 	switch (func) {
 	case OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR:
@@ -3628,19 +3628,19 @@  static void phb4_init_capp_regs(struct phb4 *p)
 static void phb4_init_capp_errors(struct phb4 *p)
 {
 	/* Init_77: TXE Error AIB Fence Enable Register */
-	out_be64(p->regs + 0x0d30,	0xdff7ff0bf7ddfff0ull);
+	phb4_write_reg(p, 0x0d30,	0xdff7ff0bf7ddfff0ull);
 
 	/* Init_86: RXE_ARB Error AIB Fence Enable Register */
-	out_be64(p->regs + 0x0db0,	0xfbffd7bbfb7fbfefull);
+	phb4_write_reg(p, 0x0db0,	0xfbffd7bbfb7fbfefull);
 
 	/* Init_95: RXE_MRG Error AIB Fence Enable Register */
-	out_be64(p->regs + 0x0e30,	0xfffffeffff7fff57ull);
+	phb4_write_reg(p, 0x0e30,	0xfffffeffff7fff57ull);
 
 	/* Init_104: RXE_TCE Error AIB Fence Enable Register */
-	out_be64(p->regs + 0x0eb0,	0xffaeffafffffffffull);
+	phb4_write_reg(p, 0x0eb0,	0xffaeffafffffffffull);
 
 	/* Init_113: PHB Error AIB Fence Enable Register */
-	out_be64(p->regs + 0x0cb0,	0x35777073ff000000ull);
+	phb4_write_reg(p, 0x0cb0,	0x35777073ff000000ull);
 }
 
 /* Power Bus Common Queue Registers
@@ -3731,12 +3731,12 @@  static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number,
 	 * Bit [0:7] XSL_DSNCTL[capiind]
 	 * Init_25 - CAPI Compare/Mask
 	 */
-	out_be64(p->regs + PHB_CAPI_CMPM,
+	phb4_write_reg(p, PHB_CAPI_CMPM,
 		 0x0200FE0000000000Ull | PHB_CAPI_CMPM_ENABLE);
 
 	if (!(p->rev == PHB4_REV_NIMBUS_DD10)) {
 		/* Init_24 - ASN Compare/Mask */
-		out_be64(p->regs + PHB_PBL_ASN_CMPM,
+		phb4_write_reg(p, PHB_PBL_ASN_CMPM,
 			 0x0400FF0000000000Ull | PHB_PBL_ASN_ENABLE);
 
 		/* PBCQ Tunnel Bar Register
@@ -3761,7 +3761,7 @@  static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number,
 	}
 
 	/* non-translate/50-bit mode */
-	out_be64(p->regs + PHB_NXLATE_PREFIX, 0x0000000000000000Ull);
+	phb4_write_reg(p, PHB_NXLATE_PREFIX, 0x0000000000000000Ull);
 
 	/* set tve no translate mode allow mmio window */
 	memset(p->tve_cache, 0x0, sizeof(p->tve_cache));
@@ -3800,7 +3800,7 @@  static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number,
 
 	phb4_ioda_sel(p, IODA3_TBL_TVT, 0, true);
 	for (i = 0; i < p->tvt_size; i++)
-		out_be64(p->regs + PHB_IODA_DATA0, p->tve_cache[i]);
+		phb4_write_reg(p, PHB_IODA_DATA0, p->tve_cache[i]);
 
 	/* set mbt bar to pass capi mmio window. First applied cleared
 	 * values to HW
@@ -3811,8 +3811,8 @@  static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number,
 	}
 	phb4_ioda_sel(p, IODA3_TBL_MBT, 0, true);
 	for (i = 0; i < p->mbt_size; i++) {
-		out_be64(p->regs + PHB_IODA_DATA0, p->mbt_cache[i][0]);
-		out_be64(p->regs + PHB_IODA_DATA0, p->mbt_cache[i][1]);
+		phb4_write_reg(p, PHB_IODA_DATA0, p->mbt_cache[i][0]);
+		phb4_write_reg(p, PHB_IODA_DATA0, p->mbt_cache[i][1]);
 	}
 
 	p->mbt_cache[0][0] = IODA3_MBT0_ENABLE |
@@ -3835,8 +3835,8 @@  static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number,
 
 	phb4_ioda_sel(p, IODA3_TBL_MBT, 0, true);
 	for (i = 0; i < p->mbt_size; i++) {
-		out_be64(p->regs + PHB_IODA_DATA0, p->mbt_cache[i][0]);
-		out_be64(p->regs + PHB_IODA_DATA0, p->mbt_cache[i][1]);
+		phb4_write_reg(p, PHB_IODA_DATA0, p->mbt_cache[i][0]);
+		phb4_write_reg(p, PHB_IODA_DATA0, p->mbt_cache[i][1]);
 	}
 
 	phb4_init_capp_errors(p);
@@ -3923,7 +3923,7 @@  static void phb4_p2p_set_initiator(struct phb4 *p, uint16_t pe_number)
 	PHBDBG(p, "Setting TVE#1 for peer-to-peer for pe %d\n", pe_number);
 	tve = PPC_BIT(51);
 	phb4_ioda_sel(p, IODA3_TBL_TVT, window_id, false);
-	out_be64(p->regs + PHB_IODA_DATA0, tve);
+	phb4_write_reg(p, PHB_IODA_DATA0, tve);
 	p->tve_cache[window_id] = tve;
 }
 
@@ -4027,29 +4027,29 @@  static const struct phb_ops phb4_ops = {
 static void phb4_init_ioda3(struct phb4 *p)
 {
 	/* Init_18 - Interrupt Notify Base Address */
-	out_be64(p->regs + PHB_INT_NOTIFY_ADDR, p->irq_port);
+	phb4_write_reg(p, PHB_INT_NOTIFY_ADDR, p->irq_port);
 
 	/* Init_19 - Interrupt Notify Base Index */
-	out_be64(p->regs + PHB_INT_NOTIFY_INDEX,
+	phb4_write_reg(p, PHB_INT_NOTIFY_INDEX,
 		 xive_get_notify_base(p->base_msi));
 
 	/* Init_19x - Not in spec: Initialize source ID */
 	PHBDBG(p, "Reset state SRC_ID: %016llx\n",
-	       in_be64(p->regs + PHB_LSI_SOURCE_ID));
-	out_be64(p->regs + PHB_LSI_SOURCE_ID,
+	       phb4_read_reg(p, PHB_LSI_SOURCE_ID));
+	phb4_write_reg(p, PHB_LSI_SOURCE_ID,
 		 SETFIELD(PHB_LSI_SRC_ID, 0ull, (p->num_irqs - 1) >> 3));
 
 	/* Init_20 - RTT BAR */
-	out_be64(p->regs + PHB_RTT_BAR, p->tbl_rtt | PHB_RTT_BAR_ENABLE);
+	phb4_write_reg(p, PHB_RTT_BAR, p->tbl_rtt | PHB_RTT_BAR_ENABLE);
 
 	/* Init_21 - PELT-V BAR */
-	out_be64(p->regs + PHB_PELTV_BAR, p->tbl_peltv | PHB_PELTV_BAR_ENABLE);
+	phb4_write_reg(p, PHB_PELTV_BAR, p->tbl_peltv | PHB_PELTV_BAR_ENABLE);
 
 	/* Init_22 - Setup M32 starting address */
-	out_be64(p->regs + PHB_M32_START_ADDR, M32_PCI_START);
+	phb4_write_reg(p, PHB_M32_START_ADDR, M32_PCI_START);
 
 	/* Init_23 - Setup PEST BAR */
-	out_be64(p->regs + PHB_PEST_BAR,
+	phb4_write_reg(p, PHB_PEST_BAR,
 		 p->tbl_pest | PHB_PEST_BAR_ENABLE);
 
 	/* Init_24 - CRW Base Address Reg */
@@ -4062,17 +4062,17 @@  static void phb4_init_ioda3(struct phb4 *p)
 	/* See enable_capi_mode() */
 
 	/* Init_27 - PCIE Outbound upper address */
-	out_be64(p->regs + PHB_M64_UPPER_BITS, 0);
+	phb4_write_reg(p, PHB_M64_UPPER_BITS, 0);
 
 	/* Init_28 - PHB4 Configuration */
-	out_be64(p->regs + PHB_PHB4_CONFIG,
+	phb4_write_reg(p, PHB_PHB4_CONFIG,
 		 PHB_PHB4C_32BIT_MSI_EN |
 		 PHB_PHB4C_64BIT_MSI_EN);
 
 	/* Init_29 - At least 256ns delay according to spec. Do a dummy
 	 * read first to flush posted writes
 	 */
-	in_be64(p->regs + PHB_PHB4_CONFIG);
+	phb4_read_reg(p, PHB_PHB4_CONFIG);
 	time_wait_us(2);
 
 	/* Init_30..41 - On-chip IODA tables init */
@@ -4166,111 +4166,111 @@  static bool phb4_init_rc_cfg(struct phb4 *p)
 static void phb4_init_errors(struct phb4 *p)
 {
 	/* Init_55..63 - PBL errors */
-	out_be64(p->regs + 0x1900,	0xffffffffffffffffull);
-	out_be64(p->regs + 0x1908,	0x0000000000000000ull);
-	out_be64(p->regs + 0x1920,	0x000000004d1780f8ull);
-	out_be64(p->regs + 0x1928,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x1900,	0xffffffffffffffffull);
+	phb4_write_reg(p, 0x1908,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x1920,	0x000000004d1780f8ull);
+	phb4_write_reg(p, 0x1928,	0x0000000000000000ull);
 	if (p->rev == PHB4_REV_NIMBUS_DD10)
-		out_be64(p->regs + 0x1930,	0xffffffffb2e87f07ull);
+		phb4_write_reg(p, 0x1930,	0xffffffffb2e87f07ull);
 	else
-		out_be64(p->regs + 0x1930,	0xffffffffb2f87f07ull);
-	out_be64(p->regs + 0x1940,	0x0000000000000000ull);
-	out_be64(p->regs + 0x1948,	0x0000000000000000ull);
-	out_be64(p->regs + 0x1950,	0x0000000000000000ull);
-	out_be64(p->regs + 0x1958,	0x0000000000000000ull);
+		phb4_write_reg(p, 0x1930,	0xffffffffb2f87f07ull);
+	phb4_write_reg(p, 0x1940,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x1948,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x1950,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x1958,	0x0000000000000000ull);
 
 	/* Init_64..72 - REGB errors */
-	out_be64(p->regs + 0x1c00,	0xffffffffffffffffull);
-	out_be64(p->regs + 0x1c08,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x1c00,	0xffffffffffffffffull);
+	phb4_write_reg(p, 0x1c08,	0x0000000000000000ull);
 	/* Enable/disable error status indicators that trigger irqs */
 	if (p->has_link) {
-		out_be64(p->regs + 0x1c20,	0x2130006efca8bc00ull);
-		out_be64(p->regs + 0x1c30,	0xde8fff91035743ffull);
+		phb4_write_reg(p, 0x1c20,	0x2130006efca8bc00ull);
+		phb4_write_reg(p, 0x1c30,	0xde8fff91035743ffull);
 	} else {
-		out_be64(p->regs + 0x1c20,	0x0000000000000000ull);
-		out_be64(p->regs + 0x1c30,	0x0000000000000000ull);
+		phb4_write_reg(p, 0x1c20,	0x0000000000000000ull);
+		phb4_write_reg(p, 0x1c30,	0x0000000000000000ull);
 	}
-	out_be64(p->regs + 0x1c28,	0x0000000000000000ull);
-	out_be64(p->regs + 0x1c40,	0x0000000000000000ull);
-	out_be64(p->regs + 0x1c48,	0x0000000000000000ull);
-	out_be64(p->regs + 0x1c50,	0x0000000000000000ull);
-	out_be64(p->regs + 0x1c58,	0x0040000000000000ull);
+	phb4_write_reg(p, 0x1c28,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x1c40,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x1c48,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x1c50,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x1c58,	0x0040000000000000ull);
 
 	/* Init_73..81 - TXE errors */
-	out_be64(p->regs + 0x0d00,	0xffffffffffffffffull);
-	out_be64(p->regs + 0x0d08,	0x0000000000000000ull);
-	out_be64(p->regs + 0x0d18,	0xffffff0fffffffffull);
-	out_be64(p->regs + 0x0d28,	0x0000400a00000000ull);
-	out_be64(p->regs + 0x0d30,	0xdff7fd01f7ddfff0ull); /* XXX CAPI has diff. value */
-	out_be64(p->regs + 0x0d40,	0x0000000000000000ull);
-	out_be64(p->regs + 0x0d48,	0x0000000000000000ull);
-	out_be64(p->regs + 0x0d50,	0x0000000000000000ull);
-	out_be64(p->regs + 0x0d58,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x0d00,	0xffffffffffffffffull);
+	phb4_write_reg(p, 0x0d08,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x0d18,	0xffffff0fffffffffull);
+	phb4_write_reg(p, 0x0d28,	0x0000400a00000000ull);
+	phb4_write_reg(p, 0x0d30,	0xdff7fd01f7ddfff0ull); /* XXX CAPI has diff. value */
+	phb4_write_reg(p, 0x0d40,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x0d48,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x0d50,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x0d58,	0x0000000000000000ull);
 
 	/* Init_82..90 - RXE_ARB errors */
-	out_be64(p->regs + 0x0d80,	0xffffffffffffffffull);
-	out_be64(p->regs + 0x0d88,	0x0000000000000000ull);
-	out_be64(p->regs + 0x0d98,	0xfffffffffbffffffull);
+	phb4_write_reg(p, 0x0d80,	0xffffffffffffffffull);
+	phb4_write_reg(p, 0x0d88,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x0d98,	0xfffffffffbffffffull);
 	if (p->rev == PHB4_REV_NIMBUS_DD10)
-		out_be64(p->regs + 0x0da8,	0xc00000b801000060ull);
+		phb4_write_reg(p, 0x0da8,	0xc00000b801000060ull);
 	else
-		out_be64(p->regs + 0x0da8,	0xc00008b801000060ull);
+		phb4_write_reg(p, 0x0da8,	0xc00008b801000060ull);
 	/*
 	 * Errata ER20161123 says we should set the top two bits in
 	 * 0x0db0 but this causes config space accesses which don't
 	 * get a response to fence the PHB. This breaks probing,
 	 * hence we don't set them here.
 	 */
-	out_be64(p->regs + 0x0db0,	0x3bffd703fa7fbf8full); /* XXX CAPI has diff. value */
-	out_be64(p->regs + 0x0dc0,	0x0000000000000000ull);
-	out_be64(p->regs + 0x0dc8,	0x0000000000000000ull);
-	out_be64(p->regs + 0x0dd0,	0x0000000000000000ull);
-	out_be64(p->regs + 0x0dd8,	0x0000000004000000ull);
+	phb4_write_reg(p, 0x0db0,	0x3bffd703fa7fbf8full); /* XXX CAPI has diff. value */
+	phb4_write_reg(p, 0x0dc0,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x0dc8,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x0dd0,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x0dd8,	0x0000000004000000ull);
 
 	/* Init_91..99 - RXE_MRG errors */
-	out_be64(p->regs + 0x0e00,	0xffffffffffffffffull);
-	out_be64(p->regs + 0x0e08,	0x0000000000000000ull);
-	out_be64(p->regs + 0x0e18,	0xffffffffffffffffull);
-	out_be64(p->regs + 0x0e28,	0x0000600000000000ull);
+	phb4_write_reg(p, 0x0e00,	0xffffffffffffffffull);
+	phb4_write_reg(p, 0x0e08,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x0e18,	0xffffffffffffffffull);
+	phb4_write_reg(p, 0x0e28,	0x0000600000000000ull);
 	if (p->rev == PHB4_REV_NIMBUS_DD10) /* XXX CAPI has diff. value */
-		out_be64(p->regs + 0x0e30,	0xffff9effff7fff57ull);
+		phb4_write_reg(p, 0x0e30,	0xffff9effff7fff57ull);
 	else
-		out_be64(p->regs + 0x0e30,	0xfffffeffff7fff57ull);
-	out_be64(p->regs + 0x0e40,	0x0000000000000000ull);
-	out_be64(p->regs + 0x0e48,	0x0000000000000000ull);
-	out_be64(p->regs + 0x0e50,	0x0000000000000000ull);
-	out_be64(p->regs + 0x0e58,	0x0000000000000000ull);
+		phb4_write_reg(p, 0x0e30,	0xfffffeffff7fff57ull);
+	phb4_write_reg(p, 0x0e40,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x0e48,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x0e50,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x0e58,	0x0000000000000000ull);
 
 	/* Init_100..108 - RXE_TCE errors */
-	out_be64(p->regs + 0x0e80,	0xffffffffffffffffull);
-	out_be64(p->regs + 0x0e88,	0x0000000000000000ull);
-	out_be64(p->regs + 0x0e98,	0xffffffffffffffffull);
+	phb4_write_reg(p, 0x0e80,	0xffffffffffffffffull);
+	phb4_write_reg(p, 0x0e88,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x0e98,	0xffffffffffffffffull);
 	if (p->rev == PHB4_REV_NIMBUS_DD10)
-		out_be64(p->regs + 0x0ea8,	0x6000000000000000ull);
+		phb4_write_reg(p, 0x0ea8,	0x6000000000000000ull);
 	else
-		out_be64(p->regs + 0x0ea8,	0x60000000c0000000ull);
-	out_be64(p->regs + 0x0eb0,	0x9faeffaf3fffffffull); /* XXX CAPI has diff. value */
-	out_be64(p->regs + 0x0ec0,	0x0000000000000000ull);
-	out_be64(p->regs + 0x0ec8,	0x0000000000000000ull);
-	out_be64(p->regs + 0x0ed0,	0x0000000000000000ull);
-	out_be64(p->regs + 0x0ed8,	0x0000000000000000ull);
+		phb4_write_reg(p, 0x0ea8,	0x60000000c0000000ull);
+	phb4_write_reg(p, 0x0eb0,	0x9faeffaf3fffffffull); /* XXX CAPI has diff. value */
+	phb4_write_reg(p, 0x0ec0,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x0ec8,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x0ed0,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x0ed8,	0x0000000000000000ull);
 
 	/* Init_109..117 - RXPHB errors */
-	out_be64(p->regs + 0x0c80,	0xffffffffffffffffull);
-	out_be64(p->regs + 0x0c88,	0x0000000000000000ull);
-	out_be64(p->regs + 0x0c98,	0xffffffffffffffffull);
-	out_be64(p->regs + 0x0ca8,	0x0000004000000000ull);
-	out_be64(p->regs + 0x0cb0,	0x35777033ff000000ull); /* XXX CAPI has diff. value */
-	out_be64(p->regs + 0x0cc0,	0x0000000000000000ull);
-	out_be64(p->regs + 0x0cc8,	0x0000000000000000ull);
-	out_be64(p->regs + 0x0cd0,	0x0000000000000000ull);
-	out_be64(p->regs + 0x0cd8,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x0c80,	0xffffffffffffffffull);
+	phb4_write_reg(p, 0x0c88,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x0c98,	0xffffffffffffffffull);
+	phb4_write_reg(p, 0x0ca8,	0x0000004000000000ull);
+	phb4_write_reg(p, 0x0cb0,	0x35777033ff000000ull); /* XXX CAPI has diff. value */
+	phb4_write_reg(p, 0x0cc0,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x0cc8,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x0cd0,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x0cd8,	0x0000000000000000ull);
 
 	/* Init_118..121 - LEM */
-	out_be64(p->regs + 0x0c00,	0x0000000000000000ull);
-	out_be64(p->regs + 0x0c30,	0xffffffffffffffffull);
-	out_be64(p->regs + 0x0c38,	0xffffffffffffffffull);
-	out_be64(p->regs + 0x0c40,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x0c00,	0x0000000000000000ull);
+	phb4_write_reg(p, 0x0c30,	0xffffffffffffffffull);
+	phb4_write_reg(p, 0x0c38,	0xffffffffffffffffull);
+	phb4_write_reg(p, 0x0c40,	0x0000000000000000ull);
 }
 
 
@@ -4295,7 +4295,7 @@  static bool phb4_wait_dlp_reset(struct phb4 *p)
 
 	PHBDBG(p, "Waiting for DLP PG reset to complete...\n");
 	for (i = 0; i < DLP_RESET_ATTEMPTS; i++) {
-		val = in_be64(p->regs + PHB_PCIE_DLP_TRAIN_CTL);
+		val = phb4_read_reg(p, PHB_PCIE_DLP_TRAIN_CTL);
 		if (!(val & PHB_PCIE_DLP_DL_PGRESET))
 			break;
 		time_wait_ms(1);
@@ -4318,40 +4318,40 @@  static void phb4_init_hw(struct phb4 *p, bool first_init)
 	 */
 
 	/* Init_2 - Mask FIRs */
-	out_be64(p->regs + PHB_LEM_ERROR_MASK,			0xffffffffffffffffull);
+	phb4_write_reg(p, PHB_LEM_ERROR_MASK,			0xffffffffffffffffull);
 
 	/* Init_3 - TCE tag enable */
-	out_be64(p->regs + PHB_TCE_TAG_ENABLE,			0xffffffffffffffffull);
+	phb4_write_reg(p, PHB_TCE_TAG_ENABLE,			0xffffffffffffffffull);
 
 	/* Init_4 - PCIE System Configuration Register
 	 *
 	 * Adjust max speed based on system config
 	 */
-	val = in_be64(p->regs + PHB_PCIE_SCR);
+	val = phb4_read_reg(p, PHB_PCIE_SCR);
 	PHBDBG(p, "Default system config: 0x%016llx\n", val);
 	val = SETFIELD(PHB_PCIE_SCR_MAXLINKSPEED, val, p->max_link_speed);
-	out_be64(p->regs + PHB_PCIE_SCR, val);
+	phb4_write_reg(p, PHB_PCIE_SCR, val);
 	PHBDBG(p, "New system config    : 0x%016llx\n",
-	       in_be64(p->regs + PHB_PCIE_SCR));
+	       phb4_read_reg(p, PHB_PCIE_SCR));
 
 	/* Init_5 - deassert CFG reset */
-	creset = in_be64(p->regs + PHB_PCIE_CRESET);
+	creset = phb4_read_reg(p, PHB_PCIE_CRESET);
 	PHBDBG(p, "Initial PHB CRESET is 0x%016llx\n", creset);
 	creset &= ~PHB_PCIE_CRESET_CFG_CORE;
-	out_be64(p->regs + PHB_PCIE_CRESET,			creset);
+	phb4_write_reg(p, PHB_PCIE_CRESET,			creset);
 
 	/* Init_6..13 - PCIE DLP Lane EQ control */
 	if (p->lane_eq) {
-		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL0, be64_to_cpu(p->lane_eq[0]));
-		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL1, be64_to_cpu(p->lane_eq[1]));
-		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL2, be64_to_cpu(p->lane_eq[2]));
-		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL3, be64_to_cpu(p->lane_eq[3]));
-		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL20, be64_to_cpu(p->lane_eq[4]));
-		out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL21, be64_to_cpu(p->lane_eq[5]));
+		phb4_write_reg(p, PHB_PCIE_LANE_EQ_CNTL0, be64_to_cpu(p->lane_eq[0]));
+		phb4_write_reg(p, PHB_PCIE_LANE_EQ_CNTL1, be64_to_cpu(p->lane_eq[1]));
+		phb4_write_reg(p, PHB_PCIE_LANE_EQ_CNTL2, be64_to_cpu(p->lane_eq[2]));
+		phb4_write_reg(p, PHB_PCIE_LANE_EQ_CNTL3, be64_to_cpu(p->lane_eq[3]));
+		phb4_write_reg(p, PHB_PCIE_LANE_EQ_CNTL20, be64_to_cpu(p->lane_eq[4]));
+		phb4_write_reg(p, PHB_PCIE_LANE_EQ_CNTL21, be64_to_cpu(p->lane_eq[5]));
 		if (p->rev == PHB4_REV_NIMBUS_DD10) {
-			out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL22,
+			phb4_write_reg(p, PHB_PCIE_LANE_EQ_CNTL22,
 				 be64_to_cpu(p->lane_eq[6]));
-			out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL23,
+			phb4_write_reg(p, PHB_PCIE_LANE_EQ_CNTL23,
 				 be64_to_cpu(p->lane_eq[7]));
 		}
 	}
@@ -4367,7 +4367,7 @@  static void phb4_init_hw(struct phb4 *p, bool first_init)
 	 */
 	creset &= ~(PHB_PCIE_CRESET_TLDLP | PHB_PCIE_CRESET_PBL);
 	creset |= PHB_PCIE_CRESET_PIPE_N;
-	out_be64(p->regs + PHB_PCIE_CRESET,			   creset);
+	phb4_write_reg(p, PHB_PCIE_CRESET,			   creset);
 
 	/* Init_16 - Wait for DLP PGRESET to clear */
 	if (!phb4_wait_dlp_reset(p))
@@ -4385,16 +4385,16 @@  static void phb4_init_hw(struct phb4 *p, bool first_init)
 	if (!pci_eeh_mmio)
 		val |= PHB_CTRLR_MMIO_EEH_DISABLE;
 
-	out_be64(p->regs + PHB_CTRLR, val);
+	phb4_write_reg(p, PHB_CTRLR, val);
 
 	/* Init_18..41 - Architected IODA3 inits */
 	phb4_init_ioda3(p);
 
 	/* Init_42..45 - Clear DLP error logs */
-	out_be64(p->regs + 0x1aa0,			0xffffffffffffffffull);
-	out_be64(p->regs + 0x1aa8,			0xffffffffffffffffull);
-	out_be64(p->regs + 0x1ab0,			0xffffffffffffffffull);
-	out_be64(p->regs + 0x1ab8,			0x0);
+	phb4_write_reg(p, 0x1aa0,			0xffffffffffffffffull);
+	phb4_write_reg(p, 0x1aa8,			0xffffffffffffffffull);
+	phb4_write_reg(p, 0x1ab0,			0xffffffffffffffffull);
+	phb4_write_reg(p, 0x1ab8,			0x0);
 
 
 	/* Init_46..54 : Init root complex config space */
@@ -4432,30 +4432,30 @@  static void phb4_init_hw(struct phb4 *p, bool first_init)
 			    PCI_CFG_STAT_RECV_PERR);
 
 	/* Init_126..130 - Re-enable error interrupts */
-	out_be64(p->regs + PHB_ERR_IRQ_ENABLE,			0xca8880cc00000000ull);
-	out_be64(p->regs + PHB_TXE_ERR_IRQ_ENABLE,		0x2008400e08200000ull);
-	out_be64(p->regs + PHB_RXE_ARB_ERR_IRQ_ENABLE,		0xc40028fc01804070ull);
-	out_be64(p->regs + PHB_RXE_MRG_ERR_IRQ_ENABLE,		0x00006100008000a8ull);
+	phb4_write_reg(p, PHB_ERR_IRQ_ENABLE,			0xca8880cc00000000ull);
+	phb4_write_reg(p, PHB_TXE_ERR_IRQ_ENABLE,		0x2008400e08200000ull);
+	phb4_write_reg(p, PHB_RXE_ARB_ERR_IRQ_ENABLE,		0xc40028fc01804070ull);
+	phb4_write_reg(p, PHB_RXE_MRG_ERR_IRQ_ENABLE,		0x00006100008000a8ull);
 	if (p->rev == PHB4_REV_NIMBUS_DD10)
-		out_be64(p->regs + PHB_RXE_TCE_ERR_IRQ_ENABLE,	0x6051005000000000ull);
+		phb4_write_reg(p, PHB_RXE_TCE_ERR_IRQ_ENABLE,	0x6051005000000000ull);
 	else
-		out_be64(p->regs + PHB_RXE_TCE_ERR_IRQ_ENABLE,	0x60510050c0000000ull);
+		phb4_write_reg(p, PHB_RXE_TCE_ERR_IRQ_ENABLE,	0x60510050c0000000ull);
 
 	/* Init_131 - Re-enable LEM error mask */
-	out_be64(p->regs + PHB_LEM_ERROR_MASK,			0x0000000000000000ull);
+	phb4_write_reg(p, PHB_LEM_ERROR_MASK,			0x0000000000000000ull);
 
 
 	/* Init_132 - Enable DMA address speculation */
-	out_be64(p->regs + PHB_TCE_SPEC_CTL,			0x0000000000000000ull);
+	phb4_write_reg(p, PHB_TCE_SPEC_CTL,			0x0000000000000000ull);
 
 	/* Init_133 - Timeout Control Register 1 */
-	out_be64(p->regs + PHB_TIMEOUT_CTRL1,			0x0018150000200000ull);
+	phb4_write_reg(p, PHB_TIMEOUT_CTRL1,			0x0018150000200000ull);
 
 	/* Init_134 - Timeout Control Register 2 */
-	out_be64(p->regs + PHB_TIMEOUT_CTRL2,			0x0000181700000000ull);
+	phb4_write_reg(p, PHB_TIMEOUT_CTRL2,			0x0000181700000000ull);
 
 	/* Init_135 - PBL Timeout Control Register */
-	out_be64(p->regs + PHB_PBL_TIMEOUT_CTRL,		0x2015000000000000ull);
+	phb4_write_reg(p, PHB_PBL_TIMEOUT_CTRL,		0x2015000000000000ull);
 
 	/* Mark the PHB as functional which enables all the various sequences */
 	p->state = PHB4_STATE_FUNCTIONAL;
@@ -4487,7 +4487,7 @@  static bool phb4_read_capabilities(struct phb4 *p)
 	PHBDBG(p, "Core revision 0x%x\n", p->rev);
 
 	/* Read EEH capabilities */
-	val = in_be64(p->regs + PHB_PHB4_EEH_CAP);
+	val = phb4_read_reg(p, PHB_PHB4_EEH_CAP);
 	if (val == 0xffffffffffffffff) {
 		PHBERR(p, "Failed to read EEH cap, PHB appears broken\n");
 		return false;
@@ -4506,7 +4506,7 @@  static bool phb4_read_capabilities(struct phb4 *p)
 	if (p->rev >= PHB4_REV_NIMBUS_DD20)
 		p->tvt_size *= 2;
 
-	val = in_be64(p->regs + PHB_PHB4_IRQ_CAP);
+	val = phb4_read_reg(p, PHB_PHB4_IRQ_CAP);
 	if (val == 0xffffffffffffffff) {
 		PHBERR(p, "Failed to read IRQ cap, PHB appears broken\n");
 		return false;
@@ -4759,9 +4759,9 @@  static int64_t phb4_ndd1_lsi_set_xive(struct irq_source *is, uint32_t isn,
 	 * will go away soon enough.
 	 */
 	if (priority == 0xff)
-		out_be64(p->regs + PHB_IODA_DATA0, IODA3_LIST_Q);
+		phb4_write_reg(p, PHB_IODA_DATA0, IODA3_LIST_Q);
 	else {
-		out_be64(p->regs + PHB_IODA_DATA0, IODA3_LIST_P);
+		phb4_write_reg(p, PHB_IODA_DATA0, IODA3_LIST_P);
 		__irq_source_eoi(is, isn);
 	}