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Date: Thu, 28 Sep 2017 13:57:56 +1300 Message-Id: <20170928005756.3938-2-kalyan.kinthada@alliedtelesis.co.nz> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170928005756.3938-1-kalyan.kinthada@alliedtelesis.co.nz> References: <20170928005756.3938-1-kalyan.kinthada@alliedtelesis.co.nz> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170927_175833_714091_9D3ADA40 X-CRM114-Status: GOOD ( 11.65 ) X-Spam-Score: -2.0 (--) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-2.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kalyan Kinthada , chris.packham@alliedtelesis.co.nz, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org When the arbitration between NOR and NAND flash is enabled the field bit[21] in the Data Flash Control Register needs to be set to 1 according to guidleine GL-5830741 mentioned in Marvell Errata document MV-S501377-00, Rev. D. This commit sets the FORCE_CSX bit to 1 for all ARMADA370 variants as the arbitration is always enabled by default. This change does not apply for pxa3xx variants because the FORCE_CSX bit does not exist/reserved on the NFCv1. The NDCR_ND_MODE conflicts with the new NDCR_FORCE_CSX but is unused so remove it along with NDCR_NAND_MODE. Signed-off-by: Kalyan Kinthada --- drivers/mtd/nand/pxa3xx_nand.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 85cff68643e0..a6a7a5af7bed 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -67,8 +67,7 @@ #define NDCR_DWIDTH_M (0x1 << 26) #define NDCR_PAGE_SZ (0x1 << 24) #define NDCR_NCSX (0x1 << 23) -#define NDCR_ND_MODE (0x3 << 21) -#define NDCR_NAND_MODE (0x0) +#define NDCR_FORCE_CSX (0x1 << 21) #define NDCR_CLR_PG_CNT (0x1 << 20) #define NFCV1_NDCR_ARB_CNTL (0x1 << 19) #define NFCV2_NDCR_STOP_ON_UNCOR (0x1 << 19) @@ -1464,6 +1463,9 @@ static int pxa3xx_nand_config_ident(struct pxa3xx_nand_info *info) info->chunk_size = PAGE_CHUNK_SIZE; info->reg_ndcr = 0x0; /* enable all interrupts */ info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; + /* Set FORCE_CSX bit for all ARMADA370 Variants. Ref#: GL-5830741 */ + if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) + info->reg_ndcr |= NDCR_FORCE_CSX; info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES); info->reg_ndcr |= NDCR_SPARE_EN; @@ -1498,6 +1500,9 @@ static void pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info) info->reg_ndcr = ndcr & ~(NDCR_INT_MASK | NDCR_ND_ARB_EN | NFCV1_NDCR_ARB_CNTL); info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; + /* Set FORCE_CSX bit for all ARMADA370 Variants. Ref#: GL-5830741 */ + if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) + info->reg_ndcr |= NDCR_FORCE_CSX; info->ndtr0cs0 = nand_readl(info, NDTR0CS0); info->ndtr1cs0 = nand_readl(info, NDTR1CS0); }