[U-Boot,v2,06/19] dts: Enable fpga-mgr node build for Arria 10 SPL

From: Tien Fong Chee <tien.fong.chee@intel.com>

From: tien.fong.chee@intel.com
To: u-boot@lists.denx.de
Date: Mon, 25 Sep 2017 16:40:02 +0800
Message-Id: <1506328815-23733-7-git-send-email-tien.fong.chee@intel.com>
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Cc: Marek Vasut <marex@denx.de>, Tien Fong Chee <tien.fong.chee@intel.com>, 
	Ching Liang See <chin.liang.see@intel.com>,
	Tien Fong <skywindctf@gmail.com>, 
	Westergteen Dalon <dalon.westergreen@intel.com>
Subject: [U-Boot] [PATCH v2 06/19] dts: Enable fpga-mgr node build for Arria
	10 SPL
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Message ID	1506328815-23733-7-git-send-email-tien.fong.chee@intel.com
State	Changes Requested
Delegated to:	Marek Vasut
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Mon, 25 Sep 2017 16:40:02 +0800 Message-Id: <1506328815-23733-7-git-send-email-tien.fong.chee@intel.com> In-Reply-To: <1506328815-23733-1-git-send-email-tien.fong.chee@intel.com> References: <1506328815-23733-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut <marex@denx.de>, Tien Fong Chee <tien.fong.chee@intel.com>, Ching Liang See <chin.liang.see@intel.com>, Tien Fong <skywindctf@gmail.com>, Westergteen Dalon <dalon.westergreen@intel.com> Subject: [U-Boot] [PATCH v2 06/19] dts: Enable fpga-mgr node build for Arria 10 SPL Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	Add FPGA, SDRAM, SPL loads U-boot & booting to console \| expand [U-Boot,v2,00/19] Add FPGA, SDRAM, SPL loads U-boot & booting to console [U-Boot,v2,01/19] ARM: socfpga: add bindings doc for arria10 fpga manager [U-Boot,v2,02/19] doc: dtbinding: Description on FPGA RBF properties at Arria 10 FPGA manager [U-Boot,v2,03/19] dts: Add FPGA bitstream properties to Arria 10 DTS [U-Boot,v2,04/19] arm: socfpga: Add Arria 10 SoCFPGA programming interface [U-Boot,v2,05/19] arm: socfpga: Enhance FPGA program write rbf data with size >= 4 bytes [U-Boot,v2,06/19] dts: Enable fpga-mgr node build for Arria 10 SPL [U-Boot,v2,07/19] fdt: Add compatible strings for Arria 10 [U-Boot,v2,08/19] fs: Enable generic filesystems interface support in SPL. [U-Boot,v2,09/19] arm: socfpga: Add drivers for programing FPGA from flash [U-Boot,v2,10/19] arm: socfpga: Rename the gen5 sdram driver to more specific name [U-Boot,v2,11/19] arm: socfpga: Add DRAM bank size initialization function [U-Boot,v2,12/19] arm: socfpga: Add DDR driver for Arria 10 [U-Boot,v2,13/19] configs: Add DDR Kconfig support for Arria 10 [U-Boot,v2,14/19] arm: socfpga: Enable build for DDR Arria 10 [U-Boot,v2,15/19] arm: socfpga: Add support to memory allocation in SPL [U-Boot,v2,16/19] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10 [U-Boot,v2,17/19] arm: socfpga: Adding clock frequency info for U-boot [U-Boot,v2,18/19] arm: socfpga: Adding SoCFPGA info for both SPL and U-boot [U-Boot,v2,19/19] arm: socfpga: Enable SPL loading U-boot to DDR and booting U-boot

[U-Boot,v2,06/19] dts: Enable fpga-mgr node build for Arria 10 SPL

Commit Message

Patch