| Message ID | 1506328815-23733-15-git-send-email-tien.fong.chee@intel.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Marek Vasut |
| Headers | show |
| Series | Add FPGA, SDRAM, SPL loads U-boot & booting to console | expand |
On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote: > From: Tien Fong Chee <tien.fong.chee@intel.com> > > This patch is for enabling the DDR support on Arria 10. > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> > --- > drivers/ddr/altera/Makefile | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile > index ac4ab85..02f8b7c 100644 > --- a/drivers/ddr/altera/Makefile > +++ b/drivers/ddr/altera/Makefile > @@ -10,4 +10,5 @@ > > ifdef CONFIG_ALTERA_SDRAM > obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o > +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o > endif > This should be part of the patch which added the sdram_arria10.c
On Isn, 2017-09-25 at 11:20 +0200, Marek Vasut wrote: > On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote: > > > > From: Tien Fong Chee <tien.fong.chee@intel.com> > > > > This patch is for enabling the DDR support on Arria 10. > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> > > --- > > drivers/ddr/altera/Makefile | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/ddr/altera/Makefile > > b/drivers/ddr/altera/Makefile > > index ac4ab85..02f8b7c 100644 > > --- a/drivers/ddr/altera/Makefile > > +++ b/drivers/ddr/altera/Makefile > > @@ -10,4 +10,5 @@ > > > > ifdef CONFIG_ALTERA_SDRAM > > obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o > > +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o > > endif > > > This should be part of the patch which added the sdram_arria10.c > Okay.
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index ac4ab85..02f8b7c 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -10,4 +10,5 @@ ifdef CONFIG_ALTERA_SDRAM obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o endif