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[07/20] target/arm: Warn about restoring to unaligned stack

Message ID 1506092407-26985-8-git-send-email-peter.maydell@linaro.org
State New
Headers show
Series ARM v8M: exception entry, exit and security | expand

Commit Message

Peter Maydell Sept. 22, 2017, 2:59 p.m. UTC
Attempting to do an exception return with an exception frame that
is not 8-aligned is UNPREDICTABLE in v8M; warn about this.
(It is not UNPREDICTABLE in v7M, and our implementation can
handle the merely-4-aligned case fine, so we don't need to
do anything except warn.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 7 +++++++
 1 file changed, 7 insertions(+)

Comments

Richard Henderson Oct. 5, 2017, 4:28 p.m. UTC | #1
On 09/22/2017 10:59 AM, Peter Maydell wrote:
> Attempting to do an exception return with an exception frame that
> is not 8-aligned is UNPREDICTABLE in v8M; warn about this.
> (It is not UNPREDICTABLE in v7M, and our implementation can
> handle the merely-4-aligned case fine, so we don't need to
> do anything except warn.)
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target/arm/helper.c | 7 +++++++
>  1 file changed, 7 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~
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Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index a2e46fb..979129e 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6403,6 +6403,13 @@  static void do_v7m_exception_exit(ARMCPU *cpu)
                                               return_to_sp_process);
         uint32_t frameptr = *frame_sp_p;
 
+        if (!QEMU_IS_ALIGNED(frameptr, 8) &&
+            arm_feature(env, ARM_FEATURE_V8)) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "M profile exception return with non-8-aligned SP "
+                          "for destination state is UNPREDICTABLE\n");
+        }
+
         /* Pop registers. TODO: make these accesses use the correct
          * attributes and address space (S/NS, priv/unpriv) and handle
          * memory transaction failures.