| Message ID | 20170922072635.32105-8-wens@csie.org |
|---|---|
| State | Accepted |
| Commit | 13ae2a40e7d458ad0c2961359c346578a305263d |
| Delegated to: | Jagannadha Sutradharudu Teki |
| Headers | show |
| Series | sunxi: A83T improvements | expand |
On Fri, Sep 22, 2017 at 07:26:33AM +0000, Chen-Yu Tsai wrote: > Only the H3/H5 SoCs have an internal PHY and its related clock and > reset controls. > > Use an #ifdef to guard the internal PHY control code block so it > can be built for other SoCs, such as the A83T or A64. > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Maxime
On Fri, Sep 22, 2017 at 2:26 AM, Chen-Yu Tsai <wens@csie.org> wrote: > Only the H3/H5 SoCs have an internal PHY and its related clock and > reset controls. > > Use an #ifdef to guard the internal PHY control code block so it > can be built for other SoCs, such as the A83T or A64. > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
On Wed, Sep 27, 2017 at 11:46 PM, Joe Hershberger <joe.hershberger@ni.com> wrote: > On Fri, Sep 22, 2017 at 2:26 AM, Chen-Yu Tsai <wens@csie.org> wrote: >> Only the H3/H5 SoCs have an internal PHY and its related clock and >> reset controls. >> >> Use an #ifdef to guard the internal PHY control code block so it >> can be built for other SoCs, such as the A83T or A64. >> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org> > > Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> This hasn't been applied yet. Can someone apply this? Jagan? Thanks ChenYu
On Fri, Nov 10, 2017 at 9:52 AM, Chen-Yu Tsai <wens@csie.org> wrote: > On Wed, Sep 27, 2017 at 11:46 PM, Joe Hershberger > <joe.hershberger@ni.com> wrote: >> On Fri, Sep 22, 2017 at 2:26 AM, Chen-Yu Tsai <wens@csie.org> wrote: >>> Only the H3/H5 SoCs have an internal PHY and its related clock and >>> reset controls. >>> >>> Use an #ifdef to guard the internal PHY control code block so it >>> can be built for other SoCs, such as the A83T or A64. >>> >>> Signed-off-by: Chen-Yu Tsai <wens@csie.org> >> >> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> > > This hasn't been applied yet. Can someone apply this? Jagan? Few emac patches on this series still under review, was this independent fix?
On Fri, Nov 10, 2017 at 2:01 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote: > On Fri, Nov 10, 2017 at 9:52 AM, Chen-Yu Tsai <wens@csie.org> wrote: >> On Wed, Sep 27, 2017 at 11:46 PM, Joe Hershberger >> <joe.hershberger@ni.com> wrote: >>> On Fri, Sep 22, 2017 at 2:26 AM, Chen-Yu Tsai <wens@csie.org> wrote: >>>> Only the H3/H5 SoCs have an internal PHY and its related clock and >>>> reset controls. >>>> >>>> Use an #ifdef to guard the internal PHY control code block so it >>>> can be built for other SoCs, such as the A83T or A64. >>>> >>>> Signed-off-by: Chen-Yu Tsai <wens@csie.org> >>> >>> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> >> >> This hasn't been applied yet. Can someone apply this? Jagan? > > Few emac patches on this series still under review, was this independent fix? I would consider it an independent fix. Nothing prevents people from manually enabling the EMAC driver on other SoCs. They will then get a build fail that this patch fixes. As for the other patches, I respin them soon enough. ChenYu
On Fri, Nov 10, 2017 at 11:34 AM, Chen-Yu Tsai <wens@csie.org> wrote: > On Fri, Nov 10, 2017 at 2:01 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >> On Fri, Nov 10, 2017 at 9:52 AM, Chen-Yu Tsai <wens@csie.org> wrote: >>> On Wed, Sep 27, 2017 at 11:46 PM, Joe Hershberger >>> <joe.hershberger@ni.com> wrote: >>>> On Fri, Sep 22, 2017 at 2:26 AM, Chen-Yu Tsai <wens@csie.org> wrote: >>>>> Only the H3/H5 SoCs have an internal PHY and its related clock and >>>>> reset controls. >>>>> >>>>> Use an #ifdef to guard the internal PHY control code block so it >>>>> can be built for other SoCs, such as the A83T or A64. >>>>> >>>>> Signed-off-by: Chen-Yu Tsai <wens@csie.org> >>>> >>>> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> >>> >>> This hasn't been applied yet. Can someone apply this? Jagan? >> >> Few emac patches on this series still under review, was this independent fix? > > I would consider it an independent fix. Nothing prevents people from > manually enabling the EMAC driver on other SoCs. They will then get > a build fail that this patch fixes. > > As for the other patches, I respin them soon enough. Applied to u-boot-sunxi/master thanks!
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 5fa1b4c170d7..0a98a04967da 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -616,6 +616,8 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv) { struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; +#ifdef CONFIG_MACH_SUNXI_H3_H5 + /* Only H3/H5 have clock controls for internal EPHY */ if (priv->use_internal_phy) { /* Set clock gating for ephy */ setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY)); @@ -623,6 +625,7 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv) /* Deassert EPHY */ setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY)); } +#endif /* Set clock gating for emac */ setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- drivers/net/sun8i_emac.c | 3 +++ 1 file changed, 3 insertions(+)