From patchwork Fri Sep 22 06:22:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shilpasri G Bhat X-Patchwork-Id: 817336 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xz3Mf4Ngyz9sNc for ; Fri, 22 Sep 2017 16:23:42 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xz3Mf21hjzDsN5 for ; Fri, 22 Sep 2017 16:23:42 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=shilpa.bhat@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xz3MW3g3bzDsMk for ; Fri, 22 Sep 2017 16:23:34 +1000 (AEST) Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v8M6J9OG131083 for ; Fri, 22 Sep 2017 02:23:31 -0400 Received: from e23smtp06.au.ibm.com (e23smtp06.au.ibm.com [202.81.31.148]) by mx0a-001b2d01.pphosted.com with ESMTP id 2d4pnnuxfh-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Fri, 22 Sep 2017 02:23:31 -0400 Received: from localhost by e23smtp06.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 22 Sep 2017 16:23:27 +1000 Received: from d23av01.au.ibm.com (d23av01.au.ibm.com [9.190.234.96]) by d23relay06.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v8M6NQbT42729570 for ; Fri, 22 Sep 2017 16:23:26 +1000 Received: from d23av01.au.ibm.com (localhost [127.0.0.1]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v8M6NRI5021446 for ; Fri, 22 Sep 2017 16:23:27 +1000 Received: from oc4502181600.in.ibm.com (oc4502181600.in.ibm.com [9.124.35.168]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v8M6NO1Y021426; Fri, 22 Sep 2017 16:23:25 +1000 From: Shilpasri G Bhat To: skiboot@lists.ozlabs.org Date: Fri, 22 Sep 2017 11:52:59 +0530 X-Mailer: git-send-email 1.8.3.1 X-TM-AS-MML: disable x-cbid: 17092206-0040-0000-0000-0000035740E6 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17092206-0041-0000-0000-00000CD807E9 Message-Id: <1506061379-23881-1-git-send-email-shilpa.bhat@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-09-22_01:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1709220088 Subject: [Skiboot] [PATCH V3] sensors: dts: Assert special wakeup on idle cores while reading temperature X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ego@linux.vnet.ibm.com MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" In P9, when a core enters a stop state, its clocks will be stopped to save power and hence we will not be able to perform a scom operation to read the DTS temperature sensor. Hence, assert a special wakeup on cores that have entered a stop state in order to successfully complete the scom operation. Signed-off-by: Shilpasri G Bhat --- Changes from V2: - Rebase on msater to use dctl_{set/clear}_special_wakeup() core/direct-controls.c | 4 +-- core/sensor.c | 2 +- hw/dts.c | 83 +++++++++++++++++++++++++++++++++++++++++--------- include/cpu.h | 3 ++ include/dts.h | 2 +- 5 files changed, 76 insertions(+), 18 deletions(-) diff --git a/core/direct-controls.c b/core/direct-controls.c index 9acdab5..1f44bc7 100644 --- a/core/direct-controls.c +++ b/core/direct-controls.c @@ -217,7 +217,7 @@ static int p9_sreset_thread(struct cpu_thread *cpu) return 0; } -static int dctl_set_special_wakeup(struct cpu_thread *t) +int dctl_set_special_wakeup(struct cpu_thread *t) { struct cpu_thread *c = t->primary; int rc = OPAL_SUCCESS; @@ -235,7 +235,7 @@ static int dctl_set_special_wakeup(struct cpu_thread *t) return rc; } -static int dctl_clear_special_wakeup(struct cpu_thread *t) +int dctl_clear_special_wakeup(struct cpu_thread *t) { struct cpu_thread *c = t->primary; int rc = OPAL_SUCCESS; diff --git a/core/sensor.c b/core/sensor.c index 57b21bc..0e2a5ca 100644 --- a/core/sensor.c +++ b/core/sensor.c @@ -28,7 +28,7 @@ static int64_t opal_sensor_read(uint32_t sensor_hndl, int token, { switch (sensor_get_family(sensor_hndl)) { case SENSOR_DTS: - return dts_sensor_read(sensor_hndl, sensor_data); + return dts_sensor_read(sensor_hndl, token, sensor_data); case SENSOR_OCC: return occ_sensor_read(sensor_hndl, sensor_data); default: diff --git a/hw/dts.c b/hw/dts.c index a10df58..2fda769 100644 --- a/hw/dts.c +++ b/hw/dts.c @@ -20,6 +20,9 @@ #include #include #include +#include +#include +#include struct dts { uint8_t valid; @@ -27,6 +30,14 @@ struct dts { int16_t temp; }; +/* + * Attributes for the core temperature sensor + */ +enum { + SENSOR_DTS_ATTR_TEMP_MAX, + SENSOR_DTS_ATTR_TEMP_TRIP +}; + /* Different sensor locations */ #define P7_CT_ZONE_LSU 0 #define P7_CT_ZONE_ISU 1 @@ -196,7 +207,7 @@ static int dts_read_core_temp_p8(uint32_t pir, struct dts *dts) * Returns the temperature as the max of all zones and a global trip * attribute. */ -static int dts_read_core_temp_p9(uint32_t pir, struct dts *dts) +static int _dts_read_core_temp_p9(u32 pir, struct dts *dts) { int32_t chip_id = pir_to_chip_id(pir); int32_t core = pir_to_core_id(pir); @@ -225,7 +236,52 @@ static int dts_read_core_temp_p9(uint32_t pir, struct dts *dts) return 0; } -static int dts_read_core_temp(uint32_t pir, struct dts *dts) +static struct timer dts_timer; +static struct dts_async_data { + struct cpu_thread *cpu; + u32 *sensor_data; + int token; + u8 attr; +} dts_async_data; + +static void dts_async_read_temp(struct timer *t __unused, void *data __unused, + u64 now __unused) +{ + struct dts dts; + int rc; + + rc = dctl_set_special_wakeup(dts_async_data.cpu); + if (rc) + prerror("Failed to set special wakeup on %d (%d)\n", + dts_async_data.cpu->pir, rc); + + rc = _dts_read_core_temp_p9(dts_async_data.cpu->pir, &dts); + if (!rc) { + if (dts_async_data.attr == SENSOR_DTS_ATTR_TEMP_MAX) + *dts_async_data.sensor_data = dts.temp; + else if (dts_async_data.attr == SENSOR_DTS_ATTR_TEMP_TRIP) + *dts_async_data.sensor_data = dts.trip; + } + + rc = opal_queue_msg(OPAL_MSG_ASYNC_COMP, NULL, NULL, + dts_async_data.token, rc); + if (rc) + prerror("Failed to queue async message\n"); + + rc = dctl_clear_special_wakeup(dts_async_data.cpu); + if (rc) + prerror("Failed to clear special wakeup on %d (%d)\n", + dts_async_data.cpu->pir, rc); +} + +static int dts_read_core_temp_p9(void) +{ + schedule_timer(&dts_timer, usecs_to_tb(1)); + return OPAL_ASYNC_COMPLETION; +} + +static int dts_read_core_temp(u32 pir, struct dts *dts, u8 attr, + int token, u32 *sensor_data) { int rc; @@ -236,8 +292,14 @@ static int dts_read_core_temp(uint32_t pir, struct dts *dts) case proc_gen_p8: rc = dts_read_core_temp_p8(pir, dts); break; - case proc_gen_p9: - rc = dts_read_core_temp_p9(pir, dts); + case proc_gen_p9: /* Asynchronus read */ + dts_async_data.attr = attr; + dts_async_data.cpu = find_cpu_by_pir(pir); + if (!dts_async_data.cpu) + return OPAL_PARAMETER; + dts_async_data.sensor_data = sensor_data; + dts_async_data.token = token; + rc = dts_read_core_temp_p9(); break; default: rc = OPAL_UNSUPPORTED; @@ -303,20 +365,12 @@ enum sensor_dts_class { }; /* - * Attributes for the core temperature sensor - */ -enum { - SENSOR_DTS_ATTR_TEMP_MAX, - SENSOR_DTS_ATTR_TEMP_TRIP -}; - -/* * Extract the centaur chip id which was truncated to fit in the * resource identifier field of the sensor handler */ #define centaur_get_id(rid) (0x80000000 | ((rid) & 0x3ff)) -int64_t dts_sensor_read(uint32_t sensor_hndl, uint32_t *sensor_data) +int64_t dts_sensor_read(u32 sensor_hndl, int token, u32 *sensor_data) { uint8_t attr = sensor_get_attr(sensor_hndl); uint32_t rid = sensor_get_rid(sensor_hndl); @@ -330,7 +384,7 @@ int64_t dts_sensor_read(uint32_t sensor_hndl, uint32_t *sensor_data) switch (sensor_get_frc(sensor_hndl)) { case SENSOR_DTS_CORE_TEMP: - rc = dts_read_core_temp(rid, &dts); + rc = dts_read_core_temp(rid, &dts, attr, token, sensor_data); break; case SENSOR_DTS_MEM_TEMP: rc = dts_read_mem_temp(centaur_get_id(rid), &dts); @@ -431,5 +485,6 @@ bool dts_sensor_create_nodes(struct dt_node *sensors) dt_add_property_string(node, "label", "Centaur"); } + init_timer(&dts_timer, dts_async_read_temp, NULL); return true; } diff --git a/include/cpu.h b/include/cpu.h index 1b622a5..24d7742 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -280,4 +280,7 @@ extern void cpu_idle_delay(unsigned long delay, unsigned long min_pm); extern void cpu_set_radix_mode(void); extern void cpu_fast_reboot_complete(void); +int dctl_set_special_wakeup(struct cpu_thread *t); +int dctl_clear_special_wakeup(struct cpu_thread *t); + #endif /* __CPU_H */ diff --git a/include/dts.h b/include/dts.h index b37919f..17e2e15 100644 --- a/include/dts.h +++ b/include/dts.h @@ -19,7 +19,7 @@ #include -extern int64_t dts_sensor_read(uint32_t sensor_hndl, uint32_t *sensor_data); +extern int64_t dts_sensor_read(u32 sensor_hndl, int token, u32 *sensor_data); extern bool dts_sensor_create_nodes(struct dt_node *sensors); #endif /* __DTS_H */