From patchwork Thu Feb 3 19:43:23 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 81705 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 0EEC6B7088 for ; Fri, 4 Feb 2011 06:55:03 +1100 (EST) Received: from localhost ([127.0.0.1]:60507 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pl5Ge-0001vJ-NS for incoming@patchwork.ozlabs.org; Thu, 03 Feb 2011 14:55:00 -0500 Received: from [140.186.70.92] (port=45595 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pl57a-0003ip-V8 for qemu-devel@nongnu.org; Thu, 03 Feb 2011 14:45:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Pl55Z-0002O6-6S for qemu-devel@nongnu.org; Thu, 03 Feb 2011 14:43:34 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:26905) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Pl55Y-0002NL-VO for qemu-devel@nongnu.org; Thu, 03 Feb 2011 14:43:33 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.69) (envelope-from ) id 1Pl55R-0000nZ-4R; Thu, 03 Feb 2011 19:43:25 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 3 Feb 2011 19:43:23 +0000 Message-Id: <1296762205-3043-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1296762205-3043-1-git-send-email-peter.maydell@linaro.org> References: <1296762205-3043-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: patches@linaro.org Subject: [Qemu-devel] [PATCH 2/4] target-arm: Clean up handling of MPIDR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The ARM cp15 register 0,c0,c0,5 is standardised in the v7 architecture as the MPIDR. Clean up its implementation to remove A9 specific handling. This commit includes fixing an error in the value returned for the MPIDR on A9, where we were erroneously claiming a cluster ID of 9. Signed-off-by: Peter Maydell --- target-arm/helper.c | 26 +++++++++++++++++++++----- 1 files changed, 21 insertions(+), 5 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 3cf9181..d46defc 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1608,12 +1608,28 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) return 0; case 3: /* TLB type register. */ return 0; /* No lockable TLB entries. */ - case 5: /* CPU ID */ - if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) { - return env->cpu_index | 0x80000900; - } else { - return env->cpu_index; + case 5: /* MPIDR */ + /* The MPIDR was standardised in v7; prior to + * this it was implemented only in the 11MPCore. + * For all other pre-v7 cores it does not exist. + */ + if (arm_feature(env, ARM_FEATURE_V7) || + ARM_CPUID(env) == ARM_CPUID_ARM11MPCORE) { + int mpidr = env->cpu_index; + /* We don't support setting cluster ID ([8..11]) + * so these bits always RAZ. + */ + if (arm_feature(env, ARM_FEATURE_V7MP)) { + mpidr |= (1 << 31); + /* Cores which are uniprocessor (non-coherent) + * but still implement the MP extensions set + * bit 30. (For instance, A9UP.) However we do + * not currently model any of those cores. + */ + } + return mpidr; } + /* otherwise fall through to the unimplemented-reg case */ default: goto bad_reg; }