[v2] npu2: hw-procedures: Enable low power mode

Message ID 1505351763-12233-1-git-send-email-arbab@linux.vnet.ibm.com
State Changes Requested
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  • [v2] npu2: hw-procedures: Enable low power mode
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Commit Message

Reza Arbab Sept. 14, 2017, 1:16 a.m.
Add a procedure which sets the NTL low power config register.

Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com>
---
v2:
* New documentation has updated the value we should set.

v1:
* http://patchwork.ozlabs.org/patch/810822/
---
 hw/npu2-hw-procedures.c | 18 +++++++++++++++++-
 include/npu2-regs.h     |  6 ++++++
 2 files changed, 23 insertions(+), 1 deletion(-)

Comments

Andrew Donnellan Sept. 14, 2017, 1:27 a.m. | #1
On 14/09/17 11:16, Reza Arbab wrote:
> Add a procedure which sets the NTL low power config register.
> 
> Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com>

Matches my documentation.

Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>

> ---
> v2:
> * New documentation has updated the value we should set.
> 
> v1:
> * http://patchwork.ozlabs.org/patch/810822/
> ---
>   hw/npu2-hw-procedures.c | 18 +++++++++++++++++-
>   include/npu2-regs.h     |  6 ++++++
>   2 files changed, 23 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c
> index 7617962..bb0769b 100644
> --- a/hw/npu2-hw-procedures.c
> +++ b/hw/npu2-hw-procedures.c
> @@ -310,9 +310,25 @@ static uint32_t phy_reset_complete(struct npu2_dev *ndev)
>   		phy_write_lane(ndev, &NPU2_PHY_TX_LANE_PDWN, lane, 0);
>   	}
>   
> +	return PROCEDURE_NEXT;
> +}
> +
> +/* Procedure 1.2.11 - Enable Low Power Mode */
> +static uint32_t enable_low_power(struct npu2_dev *ndev)
> +{
> +	uint64_t val;
> +
> +	val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_MODE_ENABLE, 0ull, 1);
> +	val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_TIMER_TICK_CONFIG, val, 5);
> +	val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_MIN_CRED_THRESH, val, 68);
> +	val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_MAX_CRED_THRESH, val, 68);
> +	val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_CNT_THRESH, val, 1280);
> +	npu2_write(ndev->npu, NPU2_NTL_LOW_POWER_CFG(ndev), val);
> +
>   	return PROCEDURE_COMPLETE;
>   }
> -DEFINE_PROCEDURE(phy_reset, phy_reset_wait, phy_reset_complete);
> +DEFINE_PROCEDURE(phy_reset, phy_reset_wait, phy_reset_complete,
> +		 enable_low_power);
>   
>   /* Procedure 1.2.6 - I/O PHY Tx Impedance Calibration */
>   static uint32_t phy_tx_zcal(struct npu2_dev *ndev)
> diff --git a/include/npu2-regs.h b/include/npu2-regs.h
> index 759404c..307e93b 100644
> --- a/include/npu2-regs.h
> +++ b/include/npu2-regs.h
> @@ -248,6 +248,12 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask);
>   #define NPU2_NTL_MISC_CFG1(ndev)		NPU2_NTLU_REG_OFFSET(ndev, 0x0C0)
>   #define NPU2_NTL_SCRATCH1(ndev)			NPU2_NTLU_REG_OFFSET(ndev, 0x0D0)
>   #define NPU2_NTL_LOW_POWER_CFG(ndev)		NPU2_NTLU_REG_OFFSET(ndev, 0x0E0)
> +#define   NPU2_NTL_LOW_POWER_CFG_MODE_ENABLE		PPC_BIT(0)
> +#define   NPU2_NTL_LOW_POWER_CFG_ONLY_MODE		PPC_BIT(1)
> +#define   NPU2_NTL_LOW_POWER_CFG_TIMER_TICK_CONFIG	PPC_BITMASK(2,7)
> +#define   NPU2_NTL_LOW_POWER_CFG_MIN_CRED_THRESH	PPC_BITMASK(8,19)
> +#define   NPU2_NTL_LOW_POWER_CFG_MAX_CRED_THRESH	PPC_BITMASK(20,31)
> +#define   NPU2_NTL_LOW_POWER_CFG_CNT_THRESH		PPC_BITMASK(32,43)
>   #define NPU2_NTL_DBG_INHIBIT_CFG(ndev)		NPU2_NTL_REG_OFFSET(ndev, 0x220)
>   #define NPU2_NTL_DISPLAY_CTL(ndev)		NPU2_NTL_REG_OFFSET(ndev, 0x280)
>   #define NPU2_NTL_DISPLAY_DATA0(ndev)		NPU2_NTL_REG_OFFSET(ndev, 0x288)
>
Reza Arbab Sept. 14, 2017, 10:25 p.m. | #2
On Thu, Sep 14, 2017 at 01:16:03AM +0000, Reza Arbab wrote:
>Add a procedure which sets the NTL low power config register.

Stewart,

Please disregard this patch for now. It has raised questions of whether 
these are the final values, and if this procedure is better separate 
than chained after phy_reset. We'll have to revisit once more is known.
Stewart Smith Sept. 15, 2017, 4:54 a.m. | #3
Reza Arbab <arbab@linux.vnet.ibm.com> writes:
> On Thu, Sep 14, 2017 at 01:16:03AM +0000, Reza Arbab wrote:
>>Add a procedure which sets the NTL low power config register.
>
> Stewart,
>
> Please disregard this patch for now. It has raised questions of whether 
> these are the final values, and if this procedure is better separate 
> than chained after phy_reset. We'll have to revisit once more is
> known.

Ok. THanks for letting me know.

Patch

diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c
index 7617962..bb0769b 100644
--- a/hw/npu2-hw-procedures.c
+++ b/hw/npu2-hw-procedures.c
@@ -310,9 +310,25 @@  static uint32_t phy_reset_complete(struct npu2_dev *ndev)
 		phy_write_lane(ndev, &NPU2_PHY_TX_LANE_PDWN, lane, 0);
 	}
 
+	return PROCEDURE_NEXT;
+}
+
+/* Procedure 1.2.11 - Enable Low Power Mode */
+static uint32_t enable_low_power(struct npu2_dev *ndev)
+{
+	uint64_t val;
+
+	val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_MODE_ENABLE, 0ull, 1);
+	val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_TIMER_TICK_CONFIG, val, 5);
+	val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_MIN_CRED_THRESH, val, 68);
+	val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_MAX_CRED_THRESH, val, 68);
+	val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_CNT_THRESH, val, 1280);
+	npu2_write(ndev->npu, NPU2_NTL_LOW_POWER_CFG(ndev), val);
+
 	return PROCEDURE_COMPLETE;
 }
-DEFINE_PROCEDURE(phy_reset, phy_reset_wait, phy_reset_complete);
+DEFINE_PROCEDURE(phy_reset, phy_reset_wait, phy_reset_complete,
+		 enable_low_power);
 
 /* Procedure 1.2.6 - I/O PHY Tx Impedance Calibration */
 static uint32_t phy_tx_zcal(struct npu2_dev *ndev)
diff --git a/include/npu2-regs.h b/include/npu2-regs.h
index 759404c..307e93b 100644
--- a/include/npu2-regs.h
+++ b/include/npu2-regs.h
@@ -248,6 +248,12 @@  void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask);
 #define NPU2_NTL_MISC_CFG1(ndev)		NPU2_NTLU_REG_OFFSET(ndev, 0x0C0)
 #define NPU2_NTL_SCRATCH1(ndev)			NPU2_NTLU_REG_OFFSET(ndev, 0x0D0)
 #define NPU2_NTL_LOW_POWER_CFG(ndev)		NPU2_NTLU_REG_OFFSET(ndev, 0x0E0)
+#define   NPU2_NTL_LOW_POWER_CFG_MODE_ENABLE		PPC_BIT(0)
+#define   NPU2_NTL_LOW_POWER_CFG_ONLY_MODE		PPC_BIT(1)
+#define   NPU2_NTL_LOW_POWER_CFG_TIMER_TICK_CONFIG	PPC_BITMASK(2,7)
+#define   NPU2_NTL_LOW_POWER_CFG_MIN_CRED_THRESH	PPC_BITMASK(8,19)
+#define   NPU2_NTL_LOW_POWER_CFG_MAX_CRED_THRESH	PPC_BITMASK(20,31)
+#define   NPU2_NTL_LOW_POWER_CFG_CNT_THRESH		PPC_BITMASK(32,43)
 #define NPU2_NTL_DBG_INHIBIT_CFG(ndev)		NPU2_NTL_REG_OFFSET(ndev, 0x220)
 #define NPU2_NTL_DISPLAY_CTL(ndev)		NPU2_NTL_REG_OFFSET(ndev, 0x280)
 #define NPU2_NTL_DISPLAY_DATA0(ndev)		NPU2_NTL_REG_OFFSET(ndev, 0x288)