From patchwork Tue Feb 1 19:17:31 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Glauber Costa X-Patchwork-Id: 81362 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 03614B70EE for ; Wed, 2 Feb 2011 06:31:31 +1100 (EST) Received: from localhost ([127.0.0.1]:39838 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PkLwc-0001iR-7j for incoming@patchwork.ozlabs.org; Tue, 01 Feb 2011 14:31:18 -0500 Received: from [140.186.70.92] (port=51195 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PkLlF-0006VD-Dh for qemu-devel@nongnu.org; Tue, 01 Feb 2011 14:19:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PkLkk-0005yv-1H for qemu-devel@nongnu.org; Tue, 01 Feb 2011 14:19:03 -0500 Received: from mx1.redhat.com ([209.132.183.28]:61234) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PkLkj-0005yd-MC for qemu-devel@nongnu.org; Tue, 01 Feb 2011 14:19:01 -0500 Received: from int-mx12.intmail.prod.int.phx2.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.25]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id p11JIxvQ020087 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Tue, 1 Feb 2011 14:19:00 -0500 Received: from virtlab1.virt.bos.redhat.com (virtlab1.virt.bos.redhat.com [10.16.72.21]) by int-mx12.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id p11JIwum020789; Tue, 1 Feb 2011 14:18:58 -0500 From: Glauber Costa To: kvm@vger.kernel.org Date: Tue, 1 Feb 2011 14:17:31 -0500 Message-Id: <1296587851-19621-1-git-send-email-glommer@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.25 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.132.183.28 Cc: mtosatti@redhat.com, qemu-devel@nongnu.org, avi@redhat.com Subject: [Qemu-devel] [PATCH] make tsc stable over migration and machine start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org If the machine is stopped, we should not record two different tsc values upon a save operation. The same problem happens with kvmclock. But kvmclock is taking a different diretion, being now seen as a separate device. Since this is unlikely to happen with the tsc, I am taking the approach here of simply registering a handler for state change, and using a per-CPUState variable that prevents double updates for the TSC. Signed-off-by: Glauber Costa --- target-i386/cpu.h | 1 + target-i386/kvm.c | 19 ++++++++++++++++++- 2 files changed, 19 insertions(+), 1 deletions(-) diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 6d619e8..7f1c4f8 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -732,6 +732,7 @@ typedef struct CPUX86State { uint32_t sipi_vector; uint32_t cpuid_kvm_features; uint32_t cpuid_svm_features; + uint8_t update_tsc; /* in order to simplify APIC support, we leave this pointer to the user */ diff --git a/target-i386/kvm.c b/target-i386/kvm.c index ecb8405..c3925be 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -302,6 +302,16 @@ void kvm_inject_x86_mce(CPUState *cenv, int bank, uint64_t status, static int _kvm_arch_init_vcpu(CPUState *env); +static void cpu_update_state(void *opaque, int running, int reason) +{ + CPUState *env = opaque; + + if (!running) { + env->update_tsc = 1; + } +} + + int kvm_arch_init_vcpu(CPUState *env) { int r; @@ -444,6 +454,8 @@ int kvm_arch_init_vcpu(CPUState *env) } #endif + qemu_add_vm_change_state_handler(cpu_update_state, env); + return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data); } @@ -1093,7 +1105,12 @@ static int kvm_get_msrs(CPUState *env) msrs[n++].index = MSR_STAR; if (kvm_has_msr_hsave_pa(env)) msrs[n++].index = MSR_VM_HSAVE_PA; - msrs[n++].index = MSR_IA32_TSC; + + if (env->update_tsc) { + msrs[n++].index = MSR_IA32_TSC; + env->update_tsc = 0; + } + #ifdef TARGET_X86_64 if (lm_capable_kernel) { msrs[n++].index = MSR_CSTAR;