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PR 47580: Fix corner case on powerpc using --with-cpu=power7

Message ID 20110201191845.GA16273@hungry-tiger.westford.ibm.com
State New
Headers show

Commit Message

Michael Meissner Feb. 1, 2011, 7:18 p.m. UTC 
On Tue, Feb 01, 2011 at 08:11:49PM +0100, Jakub Jelinek wrote:
> On Tue, Feb 01, 2011 at 02:08:44PM -0500, Michael Meissner wrote:
> > 2011-02-01  Michael Meissner  <meissner@linux.vnet.ibm.com>
> > 
> > 	PR target/47580
> > 	* config/rs6000/predicates.md (altivec_register_operand): Allow
> > 	virtaul registers.
> 
> virtual?
> 
> > --- gcc/config/rs6000/predicates.md	(revision 169484)
> > +++ gcc/config/rs6000/predicates.md	(working copy)
> > @@ -37,14 +37,14 @@ (define_predicate "altivec_register_oper
> >     (and (match_operand 0 "register_operand")
> >  	(match_test "GET_CODE (op) != REG
> >  		     || ALTIVEC_REGNO_P (REGNO (op))
> > -		     || REGNO (op) > LAST_VIRTUAL_REGISTER")))
> > +		     || REGNO (op) > FIRST_VIRTUAL_REGISTER")))
> 
> REGNO (op) > FIRST_VIRTUAL_REGISTER is strange, if you want to allow
> virtual registers, wouldn't you write REGNO (op) >= FIRST_VIRTUAL_REGISTER ?
> 
> 	Jakub

Here is the corrected patch:

2011-02-01  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/47580
	* config/rs6000/predicates.md (altivec_register_operand): Allow
	virtaul registers.
	(vsx_register_operand): Ditto.
	(vfloat_operand): Ditto.
	(vint_operand): Ditto.
	(vlogical_operand): Ditto.
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Patch

Index: gcc/config/rs6000/predicates.md
===================================================================
--- gcc/config/rs6000/predicates.md	(revision 169484)
+++ gcc/config/rs6000/predicates.md	(working copy)
@@ -37,14 +37,14 @@  (define_predicate "altivec_register_oper
    (and (match_operand 0 "register_operand")
 	(match_test "GET_CODE (op) != REG
 		     || ALTIVEC_REGNO_P (REGNO (op))
-		     || REGNO (op) > LAST_VIRTUAL_REGISTER")))
+		     || REGNO (op) >= FIRST_VIRTUAL_REGISTER")))
 
 ;; Return 1 if op is a VSX register.
 (define_predicate "vsx_register_operand"
    (and (match_operand 0 "register_operand")
 	(match_test "GET_CODE (op) != REG
 		     || VSX_REGNO_P (REGNO (op))
-		     || REGNO (op) > LAST_VIRTUAL_REGISTER")))
+		     || REGNO (op) >= FIRST_VIRTUAL_REGISTER")))
 
 ;; Return 1 if op is a vector register that operates on floating point vectors
 ;; (either altivec or VSX).
@@ -52,7 +52,7 @@  (define_predicate "vfloat_operand"
    (and (match_operand 0 "register_operand")
 	(match_test "GET_CODE (op) != REG
 		     || VFLOAT_REGNO_P (REGNO (op))
-		     || REGNO (op) > LAST_VIRTUAL_REGISTER")))
+		     || REGNO (op) >= FIRST_VIRTUAL_REGISTER")))
 
 ;; Return 1 if op is a vector register that operates on integer vectors
 ;; (only altivec, VSX doesn't support integer vectors)
@@ -60,7 +60,7 @@  (define_predicate "vint_operand"
    (and (match_operand 0 "register_operand")
 	(match_test "GET_CODE (op) != REG
 		     || VINT_REGNO_P (REGNO (op))
-		     || REGNO (op) > LAST_VIRTUAL_REGISTER")))
+		     || REGNO (op) >= FIRST_VIRTUAL_REGISTER")))
 
 ;; Return 1 if op is a vector register to do logical operations on (and, or,
 ;; xor, etc.)
@@ -68,7 +68,7 @@  (define_predicate "vlogical_operand"
    (and (match_operand 0 "register_operand")
 	(match_test "GET_CODE (op) != REG
 		     || VLOGICAL_REGNO_P (REGNO (op))
-		     || REGNO (op) > LAST_VIRTUAL_REGISTER")))
+		     || REGNO (op) >= FIRST_VIRTUAL_REGISTER")))
 
 ;; Return 1 if op is the carry register.
 (define_predicate "ca_operand"