[U-Boot,7/8] clk: rockchip: Add rk3399 Saradc clock support

Message ID 1505302438-74792-1-git-send-email-david.wu@rock-chips.com
State New
Delegated to: Philipp Tomsich
Headers show
Series
  • Add rockchip Saradc support
Related show

Commit Message

David Wu Sept. 13, 2017, 11:33 a.m.
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
Saradc integer divider control register is 8-bits width.

Signed-off-by: David Wu <david.wu@rock-chips.com>
---
 drivers/clk/rockchip/clk_rk3399.c | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

Comments

Philipp Tomsich Sept. 13, 2017, 8:07 p.m. | #1
> The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
> Saradc integer divider control register is 8-bits width.
> 
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> ---
>  drivers/clk/rockchip/clk_rk3399.c | 34 ++++++++++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich Sept. 13, 2017, 8:42 p.m. | #2
On Wed, 13 Sep 2017, David Wu wrote:

> The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
> Saradc integer divider control register is 8-bits width.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>

Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

> ---
> drivers/clk/rockchip/clk_rk3399.c | 34 ++++++++++++++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index 3edafea..5efe2c2 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -12,6 +12,7 @@
> #include <errno.h>
> #include <mapmem.h>
> #include <syscon.h>
> +#include <bitfield.h>
> #include <asm/io.h>
> #include <asm/arch/clock.h>
> #include <asm/arch/cru_rk3399.h>
> @@ -182,6 +183,7 @@ enum {
> 	/* CLKSEL_CON26 */
> 	CLK_SARADC_DIV_CON_SHIFT	= 8,
> 	CLK_SARADC_DIV_CON_MASK		= 0xff << CLK_SARADC_DIV_CON_SHIFT,

Can we use GENMASK here?

> +	CLK_SARADC_DIV_CON_WIDTH	= 8,
>
> 	/* CLKSEL_CON27 */
> 	CLK_TSADC_SEL_X24M		= 0x0,
> @@ -860,6 +862,32 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
>
> 	return set_rate;
> }
> +
> +static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
> +{
> +	u32 div, val;
> +
> +	val = readl(&cru->clksel_con[26]);
> +	div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
> +			       CLK_SARADC_DIV_CON_WIDTH);
> +
> +	return DIV_TO_RATE(OSC_HZ, div);
> +}
> +
> +static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz)
> +{
> +	int src_clk_div;
> +
> +	src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
> +	assert(src_clk_div < 128);
> +
> +	rk_clrsetreg(&cru->clksel_con[26],
> +		     CLK_SARADC_DIV_CON_MASK,
> +		     src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
> +
> +	return rk3399_saradc_get_clk(cru);
> +}
> +
> static ulong rk3399_clk_get_rate(struct clk *clk)
> {
> 	struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
> @@ -895,6 +923,9 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
> 		break;
> 	case PCLK_EFUSE1024NS:
> 		break;
> +	case SCLK_SARADC:
> +		rate = rk3399_saradc_get_clk(priv->cru);
> +		break;
> 	default:
> 		return -ENOENT;
> 	}
> @@ -943,6 +974,9 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
> 		break;
> 	case PCLK_EFUSE1024NS:
> 		break;
> +	case SCLK_SARADC:
> +		ret = rk3399_saradc_set_clk(priv->cru, rate);
> +		break;
> 	default:
> 		return -ENOENT;
> 	}
>

Patch

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 3edafea..5efe2c2 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -12,6 +12,7 @@ 
 #include <errno.h>
 #include <mapmem.h>
 #include <syscon.h>
+#include <bitfield.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/cru_rk3399.h>
@@ -182,6 +183,7 @@  enum {
 	/* CLKSEL_CON26 */
 	CLK_SARADC_DIV_CON_SHIFT	= 8,
 	CLK_SARADC_DIV_CON_MASK		= 0xff << CLK_SARADC_DIV_CON_SHIFT,
+	CLK_SARADC_DIV_CON_WIDTH	= 8,
 
 	/* CLKSEL_CON27 */
 	CLK_TSADC_SEL_X24M		= 0x0,
@@ -860,6 +862,32 @@  static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
 
 	return set_rate;
 }
+
+static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
+{
+	u32 div, val;
+
+	val = readl(&cru->clksel_con[26]);
+	div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
+			       CLK_SARADC_DIV_CON_WIDTH);
+
+	return DIV_TO_RATE(OSC_HZ, div);
+}
+
+static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz)
+{
+	int src_clk_div;
+
+	src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
+	assert(src_clk_div < 128);
+
+	rk_clrsetreg(&cru->clksel_con[26],
+		     CLK_SARADC_DIV_CON_MASK,
+		     src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
+
+	return rk3399_saradc_get_clk(cru);
+}
+
 static ulong rk3399_clk_get_rate(struct clk *clk)
 {
 	struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
@@ -895,6 +923,9 @@  static ulong rk3399_clk_get_rate(struct clk *clk)
 		break;
 	case PCLK_EFUSE1024NS:
 		break;
+	case SCLK_SARADC:
+		rate = rk3399_saradc_get_clk(priv->cru);
+		break;
 	default:
 		return -ENOENT;
 	}
@@ -943,6 +974,9 @@  static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
 		break;
 	case PCLK_EFUSE1024NS:
 		break;
+	case SCLK_SARADC:
+		ret = rk3399_saradc_set_clk(priv->cru, rate);
+		break;
 	default:
 		return -ENOENT;
 	}