diff mbox series

[U-Boot,v6,4/9] ARM: at91: spl: Add mck function to lower rate while switching

Message ID 20170913065854.26134-5-wenyou.yang@microchip.com
State Accepted
Commit 2b21cf55cc767bc1303f22c3f6f7b9d6f0845c02
Delegated to: Tom Rini
Headers show
Series board: atmel: Add new board SAMA5D27-SOM1-EK board. | expand

Commit Message

Wenyou Yang Sept. 13, 2017, 6:58 a.m. UTC 
Refer to the commit 70f8c8316ad(PMC: add new mck function to lower
rate while switching) from AT91Bootstrap.

While switching to a lower clock source, we must switch the clock
source first instead of last. Otherwise, we could end up with
too high frequency on internal bus and peripherals.
This happens on SAMA5D2 as exitting from the ROM code.

Add a function pmc_mck_init_down() to allow this sequence.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---

Changes in v6:
 - Add function comments for at91_mck_init_down().

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/mach-at91/armv7/clock.c              | 42 +++++++++++++++++++++++++++
 arch/arm/mach-at91/include/mach/at91_common.h |  1 +
 2 files changed, 43 insertions(+)

Comments

Tom Rini Sept. 15, 2017, 12:47 a.m. UTC | #1 
On Wed, Sep 13, 2017 at 02:58:49PM +0800, Wenyou Yang wrote:

> Refer to the commit 70f8c8316ad(PMC: add new mck function to lower
> rate while switching) from AT91Bootstrap.
> 
> While switching to a lower clock source, we must switch the clock
> source first instead of last. Otherwise, we could end up with
> too high frequency on internal bus and peripherals.
> This happens on SAMA5D2 as exitting from the ROM code.
> 
> Add a function pmc_mck_init_down() to allow this sequence.
> 
> Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>

Applied to u-boot/master, thanks!
diff mbox series

Patch

diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c
index 2e55953799..51c5e80be7 100644
--- a/arch/arm/mach-at91/armv7/clock.c
+++ b/arch/arm/mach-at91/armv7/clock.c
@@ -150,6 +150,48 @@  void at91_mck_init(u32 mckr)
 		;
 }
 
+/*
+ * For the Master Clock Controller Register(MCKR), while switching
+ * to a lower clock source, we must switch the clock source first
+ * instead of last. Otherwise, we could end up with too high frequency
+ * on the internal bus and peripherals.
+ */
+void at91_mck_init_down(u32 mckr)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	u32 tmp;
+
+	tmp = readl(&pmc->mckr);
+	tmp &= (~AT91_PMC_MCKR_CSS_MASK);
+	tmp |= (mckr & AT91_PMC_MCKR_CSS_MASK);
+	writel(tmp, &pmc->mckr);
+
+	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+		;
+
+#ifdef CPU_HAS_H32MXDIV
+	tmp = readl(&pmc->mckr);
+	tmp &= (~AT91_PMC_MCKR_H32MXDIV);
+	tmp |= (mckr & AT91_PMC_MCKR_H32MXDIV);
+	writel(tmp, &pmc->mckr);
+#endif
+
+	tmp = readl(&pmc->mckr);
+	tmp &= (~AT91_PMC_MCKR_PLLADIV_MASK);
+	tmp |= (mckr & AT91_PMC_MCKR_PLLADIV_MASK);
+	writel(tmp, &pmc->mckr);
+
+	tmp = readl(&pmc->mckr);
+	tmp &= (~AT91_PMC_MCKR_MDIV_MASK);
+	tmp |= (mckr & AT91_PMC_MCKR_MDIV_MASK);
+	writel(tmp, &pmc->mckr);
+
+	tmp = readl(&pmc->mckr);
+	tmp &= (~AT91_PMC_MCKR_PRES_MASK);
+	tmp |= (mckr & AT91_PMC_MCKR_PRES_MASK);
+	writel(tmp, &pmc->mckr);
+}
+
 int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div)
 {
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
diff --git a/arch/arm/mach-at91/include/mach/at91_common.h b/arch/arm/mach-at91/include/mach/at91_common.h
index 5416eb455d..0b09ce7b2e 100644
--- a/arch/arm/mach-at91/include/mach/at91_common.h
+++ b/arch/arm/mach-at91/include/mach/at91_common.h
@@ -25,6 +25,7 @@  void at91_lcd_hw_init(void);
 void at91_plla_init(u32 pllar);
 void at91_pllb_init(u32 pllar);
 void at91_mck_init(u32 mckr);
+void at91_mck_init_down(u32 mckr);
 void at91_pmc_init(void);
 void mem_init(void);
 void at91_phy_reset(void);