From patchwork Wed Sep 13 06:58:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenyou Yang X-Patchwork-Id: 813186 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xsXhK5yVfz9sNV for ; Wed, 13 Sep 2017 17:04:01 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id A118FC22212; Wed, 13 Sep 2017 07:02:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.3 required=5.0 tests=RCVD_IN_DNSWL_MED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 39885C224D2; Wed, 13 Sep 2017 07:02:09 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C55D6C224D2; Wed, 13 Sep 2017 07:01:07 +0000 (UTC) Received: from DVREDG02.corp.atmel.com (nasmtp01.atmel.com [192.199.1.246]) by lists.denx.de (Postfix) with ESMTPS id 6A5F9C223E5 for ; Wed, 13 Sep 2017 07:01:01 +0000 (UTC) Received: from apsmtp01.atmel.com (10.168.254.31) by DVREDG02.corp.atmel.com (10.42.103.31) with Microsoft SMTP Server (TLS) id 14.3.235.1; Wed, 13 Sep 2017 01:00:11 -0600 Received: from shaarm01.corp.atmel.com (10.168.254.13) by apsmtp01.atmel.com (10.168.254.31) with Microsoft SMTP Server id 14.3.235.1; Wed, 13 Sep 2017 15:04:34 +0800 From: Wenyou Yang To: U-Boot Mailing List Date: Wed, 13 Sep 2017 14:58:50 +0800 Message-ID: <20170913065854.26134-6-wenyou.yang@microchip.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170913065854.26134-1-wenyou.yang@microchip.com> References: <20170913065854.26134-1-wenyou.yang@microchip.com> MIME-Version: 1.0 Cc: Marek Vasut , Tom Rini Subject: [U-Boot] [PATCH v6 5/9] board: sama5d2_xplained: Make SPL work on spiflash X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Because before switching to a lower clock source, we must switch the clock source first instead of last. So before configuring the PMC_MCKR register, invoke at91_mck_init_down() first. As said in datasheet, the the size of SPL must not exceed the maximum size allowed(64Kbytes). Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass --- Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None board/atmel/sama5d2_xplained/sama5d2_xplained.c | 10 ++++++++++ include/configs/sama5d2_xplained.h | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index 7e0cb4228f..5758653030 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -247,6 +247,16 @@ void at91_pmc_init(void) struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; u32 tmp; + /* + * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz + * so we need to slow down and configure MCKR accordingly. + * This is why we have a special flavor of the switching function. + */ + tmp = AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_MAIN; + at91_mck_init_down(tmp); + tmp = AT91_PMC_PLLAR_29 | AT91_PMC_PLLXR_PLLCOUNT(0x3f) | AT91_PMC_PLLXR_MUL(82) | diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h index 891218d83e..aedd5684c4 100644 --- a/include/configs/sama5d2_xplained.h +++ b/include/configs/sama5d2_xplained.h @@ -61,7 +61,7 @@ /* SPL */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x200000 -#define CONFIG_SPL_MAX_SIZE 0x18000 +#define CONFIG_SPL_MAX_SIZE 0x10000 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000