From patchwork Mon Sep 11 21:17:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thor Thayer X-Patchwork-Id: 812622 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-i2c-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xrgfB57Sbz9s8J for ; Tue, 12 Sep 2017 07:14:10 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751392AbdIKVOI (ORCPT ); Mon, 11 Sep 2017 17:14:08 -0400 Received: from mga14.intel.com ([192.55.52.115]:63890 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751014AbdIKVOI (ORCPT ); Mon, 11 Sep 2017 17:14:08 -0400 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Sep 2017 14:14:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,379,1500966000"; d="scan'208";a="1171224528" Received: from tthayer-hp-z620-workstation.an.intel.com ([10.122.105.144]) by orsmga001.jf.intel.com with ESMTP; 11 Sep 2017 14:14:06 -0700 From: thor.thayer@linux.intel.com To: wsa@the-dreams.de, robh+dt@kernel.org, mark.rutland@arm.com, thor.thayer@linux.intel.com, andy.shevchenko@gmail.com Cc: davem@davemloft.net, gregkh@linuxfoundation.org, mchehab@kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [[RESEND]PATCHv6 1/2] dt-bindings: i2c: Add Altera I2C Controller Date: Mon, 11 Sep 2017 16:17:19 -0500 Message-Id: <1505164640-26413-1-git-send-email-thor.thayer@linux.intel.com> X-Mailer: git-send-email 2.7.4 Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Thor Thayer Add the documentation to support the Altera synthesizable logic I2C Controller in FPGA. Signed-off-by: Thor Thayer Acked-by: Rob Herring --- v2 Change the subject to identify dt-bindings Add synthesizable logic to description. Change compatible string to "altr,softip-i2c" Make description of clock phandle singular since 1 clock. Remove altr, from fifo-size Specify fifo-size is in bytes. v3 Add version to compatible string "altr,softip-i2c-v1.0" Add for use in FPGA in description. v4 No Change - Add Acked-by v5-6 No Change --- .../devicetree/bindings/i2c/i2c-altera.txt | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-altera.txt diff --git a/Documentation/devicetree/bindings/i2c/i2c-altera.txt b/Documentation/devicetree/bindings/i2c/i2c-altera.txt new file mode 100644 index 000000000000..767664f448ec --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-altera.txt @@ -0,0 +1,39 @@ +* Altera I2C Controller +* This is Altera's synthesizable logic block I2C Controller for use +* in Altera's FPGAs. + +Required properties : + - compatible : should be "altr,softip-i2c-v1.0" + - reg : Offset and length of the register set for the device + - interrupts : where IRQ is the interrupt number. + - clocks : phandle to input clock. + - #address-cells = <1>; + - #size-cells = <0>; + +Recommended properties : + - clock-frequency : desired I2C bus clock frequency in Hz. + +Optional properties : + - fifo-size : Size of the RX and TX FIFOs in bytes. + - Child nodes conforming to i2c bus binding + +Example : + + i2c@100080000 { + compatible = "altr,softip-i2c-v1.0"; + reg = <0x00000001 0x00080000 0x00000040>; + interrupt-parent = <&intc>; + interrupts = <0 43 4>; + clocks = <&clk_0>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + fifo-size = <4>; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; + }; +