Patchwork [U-Boot,2/6] powerpc/85xx: add TPL support

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Submitter Haiying Wang
Date Jan. 31, 2011, 6:41 p.m.
Message ID <1296499317-26616-3-git-send-email-Haiying.Wang@freescale.com>
Download mbox | patch
Permalink /patch/81208/
State Superseded
Headers show

Comments

Haiying Wang - Jan. 31, 2011, 6:41 p.m.
From: Haiying Wang <Haiying.Wang@freescale.com>

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/cpu.c           |    7 ++
 arch/powerpc/cpu/mpc85xx/cpu_init_nand.c |   22 ++++++-
 arch/powerpc/cpu/mpc85xx/start.S         |   12 ++--
 arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds  |   99 ++++++++++++++++++++++++++++++
 4 files changed, 132 insertions(+), 8 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds

Patch

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 1aad2ba..e923547 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -296,6 +296,12 @@  void mpc85xx_reginfo(void)
 #ifndef CONFIG_FSL_CORENET
 phys_size_t initdram(int board_type)
 {
+#if defined(CONFIG_HAS_TPL) && !defined(CONFIG_IN_TPL)
+	/* ddr has been initialized in tpl boot stage thus we only need
+	 * to get the ddr dram size for the final uboot.
+	 */
+	return fsl_ddr_sdram_size();
+#else
 	phys_size_t dram_size = 0;
 
 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
@@ -342,6 +348,7 @@  phys_size_t initdram(int board_type)
 
 	puts("DDR: ");
 	return dram_size;
+#endif /* CONFIG_HAS_TPL */
 }
 #endif
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
index 8fb27ab..65c32d9 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
@@ -1,5 +1,5 @@ 
 /*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009 - 2011 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -23,6 +23,8 @@ 
 #include <common.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void cpu_init_f(void)
 {
 	fsl_lbc_t *lbc = LBC_BASE_ADDR;
@@ -40,7 +42,8 @@  void cpu_init_f(void)
 #error  CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined
 #endif
 
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) \
+	&& !defined(CONFIG_IN_TPL)
 	ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
 	char *l2srbar;
 	int i;
@@ -60,4 +63,19 @@  void cpu_init_f(void)
 	for (i = 0; i < CONFIG_SYS_L2_SIZE; i++)
 		l2srbar[i] = 0;
 #endif
+#ifdef CONFIG_IN_TPL
+	init_used_tlb_cams();
+#endif
+}
+
+#ifdef CONFIG_IN_TPL
+/*
+ * Because the primary cpu's info is enough for the 2nd stage,  we define the
+ * cpu number to 1 so as to keep code size for 2nd stage binary as small as
+ * possible.
+ */
+int cpu_numcores()
+{
+	return 1;
 }
+#endif /* CONFIG_IN_TPL */
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index fa98af6..5496fc4 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -58,12 +58,12 @@ 
 	GOT_ENTRY(_GOT2_TABLE_)
 	GOT_ENTRY(_FIXUP_TABLE_)
 
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_IN_TPL)
 	GOT_ENTRY(_start)
 	GOT_ENTRY(_start_of_vectors)
 	GOT_ENTRY(_end_of_vectors)
 	GOT_ENTRY(transfer_to_handler)
-#endif
+#endif /* !CONFIG_NAND_SPL && !CONFIG_IN_TPL*/
 
 	GOT_ENTRY(__init_end)
 	GOT_ENTRY(_end)
@@ -435,7 +435,7 @@  _start_cont:
 
 	/* NOTREACHED - board_init_f() does not return */
 
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_IN_TPL)
 	. = EXC_OFF_SYS_RESET
 	.globl	_start_of_vectors
 _start_of_vectors:
@@ -877,7 +877,7 @@  in32:
 in32r:
 	lwbrx	r3,r0,r3
 	blr
-#endif  /* !CONFIG_NAND_SPL */
+#endif  /* !CONFIG_NAND_SPL && !CONFIG_IN_TPL */
 
 /*------------------------------------------------------------------------------*/
 
@@ -1067,7 +1067,7 @@  clear_bss:
 	mr	r4,r10		/* Destination Address		*/
 	bl	board_init_r
 
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_IN_TPL)
 	/*
 	 * Copy exception vector code to low memory
 	 *
@@ -1207,4 +1207,4 @@  setup_ivors:
 
 #include "fixed_ivor.S"
 	blr
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !CONFIG_NAND_SPL && !CONFIG_IN_TPL */
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds
new file mode 100644
index 0000000..d8ff62b
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds
@@ -0,0 +1,99 @@ 
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .text      :
+  {
+    *(.text*)
+   } :text
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  } :text
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+ .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  .bootpg ADDR(.text) - 0x1000 :
+  {
+    start.o	KEEP(*(.bootpg))
+  } :text = 0xffff
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss*)
+   *(.bss*)
+   *(COMMON)
+  } :bss
+
+  . = ALIGN(4);
+  _end = . ;
+  PROVIDE (end = .);
+}