From patchwork Sat Sep 9 01:53:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brendan Higgins X-Patchwork-Id: 811902 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.b="JXj8ITOc"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xpy0G6tmwz9sRY for ; Sat, 9 Sep 2017 11:53:50 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757355AbdIIBxV (ORCPT ); Fri, 8 Sep 2017 21:53:21 -0400 Received: from mail-pg0-f44.google.com ([74.125.83.44]:33928 "EHLO mail-pg0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757342AbdIIBxT (ORCPT ); Fri, 8 Sep 2017 21:53:19 -0400 Received: by mail-pg0-f44.google.com with SMTP id q68so7407251pgq.1 for ; Fri, 08 Sep 2017 18:53:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cl+AUacOdoeIdqOu4fU2kbL6UrkmQ1es2PdHpGU0JjY=; b=JXj8ITOcFs4B/rSDt+1MCKc3WZxKRXjC2aSgFvEVcgTv/NSkjNHZ8boNXS4O/OFwSC ela6VoJFV9AR1WuzQt9dfufV+OQt1jbVeExXzvKA90YzssYn0RsE27N9Y1rGKdx5GWaG umo15byy6DgknoO6g5bLUFVQKoVoXadxA2iT09isvEABNKHSFr1nwYqyXvyXea/Cj9bY 47VTh48ow+vrDODFtl3XoReK2lRbIkmvEp+9wF3+ivyVJJpIzKf38ixbvixIbSp6eTXF eyukDVEY/0lWQZoTRfA5uUp41os3DMio5e9drZMlUlAZ3BR9bvB3zoAhZGAyjHkvl4Id /3bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cl+AUacOdoeIdqOu4fU2kbL6UrkmQ1es2PdHpGU0JjY=; b=phtwMaQCsPlMjIWqoab+BuEAvmxwzy/UFUAuOUo6UmDvJGXpezIQrsa9U89EgwDVZ4 nQA9jEKUBhd1jQap3Y2N+hFPnl7KvSHC21B7C2iS3/ZsMzN0wS54DjGohlM2UBFnpHHp hBTzafssUumlqJVXt5u+upKc67zqKD9dkfos0Hps0DopvuPsylVPVvXtmm0tcdVbHDS7 yrHRjsxy1/D9gqwc7WYKMON0yMKEdm+7O77I8D31uA2YgUVgpd/ziEoPv6OXyAhzokeY oWdNOfermv2A0XnQyYuxyI/IxrSG8yJjDp/OSF1h9QMAVCRcUC/zCUMyHH8qEKpasYIh LPKA== X-Gm-Message-State: AHPjjUgUK/ZT4NdoJWsBLxgObztHfZkw7Rnkww7KkSw8rqd5uVnOih7+ QRNiH4uk5Q+DYcgk X-Google-Smtp-Source: ADKCNb4DM6GPwagAHDAKf/co3CuPzanzRFnCSPLlKXB1pkPsHvPeEK81NAW8ieEtrja62PBrOic+9g== X-Received: by 10.84.210.37 with SMTP id z34mr5459078plh.434.1504921998351; Fri, 08 Sep 2017 18:53:18 -0700 (PDT) Received: from mactruck.svl.corp.google.com ([100.123.242.94]) by smtp.gmail.com with ESMTPSA id z15sm5090132pgs.41.2017.09.08.18.53.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Sep 2017 18:53:17 -0700 (PDT) From: Brendan Higgins To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, avifishman70@gmail.com, tmaimon77@gmail.com, raltherr@google.com, f.fainelli@gmail.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, openbmc@lists.ozlabs.org, Brendan Higgins Subject: [PATCH v5 2/3] arm: dts: add Nuvoton NPCM750 device tree Date: Fri, 8 Sep 2017 18:53:07 -0700 Message-Id: <20170909015308.30001-3-brendanhiggins@google.com> X-Mailer: git-send-email 2.14.1.581.gf28d330327-goog In-Reply-To: <20170909015308.30001-1-brendanhiggins@google.com> References: <20170909015308.30001-1-brendanhiggins@google.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a common device tree for all Nuvoton NPCM750 BMCs and a board specific device tree for the NPCM750 (Poleg) evaluation board. Signed-off-by: Brendan Higgins Reviewed-by: Tomer Maimon Reviewed-by: Avi Fishman Reviewed-by: Joel Stanley Tested-by: Tomer Maimon Tested-by: Avi Fishman --- .../arm/cpu-enable-method/nuvoton,npcm7xx-smp | 42 +++++ .../devicetree/bindings/arm/npcm/npcm.txt | 6 + arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 57 +++++++ arch/arm/boot/dts/nuvoton-npcm750.dtsi | 177 +++++++++++++++++++++ include/dt-bindings/clock/nuvoton,npcm7xx-clks.h | 39 +++++ 5 files changed, 321 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp create mode 100644 Documentation/devicetree/bindings/arm/npcm/npcm.txt create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-evb.dts create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clks.h diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp new file mode 100644 index 000000000000..e81f85b400cf --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp @@ -0,0 +1,42 @@ +========================================================= +Secondary CPU enable-method "nuvoton,npcm7xx-smp" binding +========================================================= + +To apply to all CPUs, a single "nuvoton,npcm7xx-smp" enable method should be +defined in the "cpus" node. + +Enable method name: "nuvoton,npcm7xx-smp" +Compatible machines: "nuvoton,npcm750" +Compatible CPUs: "arm,cortex-a9" +Related properties: (none) + +Note: +This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and +"nuvoton,npcm750-gcr". + +Example: + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "nuvoton,npcm7xx-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.txt b/Documentation/devicetree/bindings/arm/npcm/npcm.txt new file mode 100644 index 000000000000..2d87d9ecea85 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/npcm/npcm.txt @@ -0,0 +1,6 @@ +NPCM Platforms Device Tree Bindings +----------------------------------- +NPCM750 SoC +Required root node properties: + - compatible = "nuvoton,npcm750"; + diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts new file mode 100644 index 000000000000..e54a870d3ee0 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts @@ -0,0 +1,57 @@ +/* + * DTS file for all NPCM750 SoCs + * + * Copyright 2012 Tomer Maimon + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "nuvoton-npcm750.dtsi" + +/ { + model = "Nuvoton npcm750 Development Board (Device Tree)"; + compatible = "nuvoton,npcm750"; + + chosen { + stdout-path = &serial3; + bootargs = "earlyprintk=serial,serial3,115200"; + }; + + memory { + reg = <0 0x40000000>; + }; + + cpus { + enable-method = "nuvoton,npcm7xx-smp"; + }; +}; + +&clk { + status = "okay"; +}; + +&watchdog1 { + status = "okay"; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi new file mode 100644 index 000000000000..bca96b3ae9d3 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi @@ -0,0 +1,177 @@ +/* + * DTSi file for the NPCM750 SoC + * + * Copyright 2012 Tomer Maimon + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "skeleton.dtsi" +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + + gcr: gcr@f0800000 { + compatible = "nuvoton,npcm750-gcr", "syscon", + "simple-mfd"; + reg = <0xf0800000 0x1000>; + }; + + scu: scu@f03fe000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xf03fe000 0x1000>; + }; + + l2: l2-cache@f03fc000 { + compatible = "arm,pl310-cache"; + reg = <0xf03fc000 0x1000>; + interrupts = <0 21 4>; + cache-unified; + cache-level = <2>; + clocks = <&clk NPCM7XX_CLK_AXI>; + }; + + gic: interrupt-controller@f03ff000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xf03ff000 0x1000>, + <0xf03fe100 0x100>; + }; + + clk: clock-controller@f0801000 { + compatible = "nuvoton,npcm750-clk"; + #clock-cells = <1>; + reg = <0xf0801000 0x1000>; + }; + + /* external clock signal rg1refck, supplied by the phy */ + clk-rg1refck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + /* external clock signal rg2refck, supplied by the phy */ + clk-rg2refck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clk-xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + timer@f03fe600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf03fe600 0x20>; + interrupts = <1 13 0x304>; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + timer0: timer@f0000000 { + compatible = "nuvoton,npcm750-timer"; + interrupts = <0 32 4>; + reg = <0xf0000000 0x1000>; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + watchdog0: watchdog@f0008000 { + compatible = "nuvoton,npcm750-wdt"; + interrupts = <0 47 4>; + reg = <0xf0008000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + watchdog1: watchdog@f0009000 { + compatible = "nuvoton,npcm750-wdt"; + interrupts = <0 48 4>; + reg = <0xf0009000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + watchdog2: watchdog@f000a000 { + compatible = "nuvoton,npcm750-wdt"; + interrupts = <0 49 4>; + reg = <0xf000a000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + serial0: serial0@f0001000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0xf0001000 0x1000>; + clocks = <&clk NPCM7XX_CLK_UART_CORE>; + interrupts = <0 2 4>; + status = "disabled"; + }; + + serial1: serial1@f0002000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0xf0002000 0x1000>; + clocks = <&clk NPCM7XX_CLK_UART_CORE>; + interrupts = <0 3 4>; + status = "disabled"; + }; + + serial2: serial2@f0003000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0xf0003000 0x1000>; + clocks = <&clk NPCM7XX_CLK_UART_CORE>; + interrupts = <0 4 4>; + status = "disabled"; + }; + + serial3: serial3@f0004000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0xf0004000 0x1000>; + clocks = <&clk NPCM7XX_CLK_UART_CORE>; + interrupts = <0 5 4>; + status = "disabled"; + }; + }; +}; diff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h new file mode 100644 index 000000000000..c69d3bbf7e42 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2016 Nuvoton Technologies, tali.perry@nuvoton.com + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + */ + +#ifndef _DT_BINDINGS_CLK_NPCM7XX_H +#define _DT_BINDINGS_CLK_NPCM7XX_H + +#define NPCM7XX_CLK_PLL0 0 +#define NPCM7XX_CLK_PLL1 1 +#define NPCM7XX_CLK_PLL2 2 +#define NPCM7XX_CLK_GFX 3 +#define NPCM7XX_CLK_APB1 4 +#define NPCM7XX_CLK_APB2 5 +#define NPCM7XX_CLK_APB3 6 +#define NPCM7XX_CLK_APB4 7 +#define NPCM7XX_CLK_APB5 8 +#define NPCM7XX_CLK_MC 9 +#define NPCM7XX_CLK_CPU 10 +#define NPCM7XX_CLK_SPI0 11 +#define NPCM7XX_CLK_SPI3 12 +#define NPCM7XX_CLK_SPIX 13 +#define NPCM7XX_CLK_UART_CORE 14 +#define NPCM7XX_CLK_TIMER 15 +#define NPCM7XX_CLK_HOST_UART 16 +#define NPCM7XX_CLK_MMC 17 +#define NPCM7XX_CLK_SDHC 18 +#define NPCM7XX_CLK_ADC 19 +#define NPCM7XX_CLK_GFX_MEM 20 +#define NPCM7XX_CLK_USB_BRIDGE 21 +#define NPCM7XX_CLK_AXI 22 +#define NPCM7XX_CLK_AHB 23 +#define NPCM7XX_CLK_EMC 24 +#define NPCM7XX_CLK_GMAC 25 + +#endif