From patchwork Fri Sep 8 15:35:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Izard X-Patchwork-Id: 811664 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="SYkaLzzz"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xphX24qgVz9t3F for ; Sat, 9 Sep 2017 01:46:58 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756590AbdIHPg0 (ORCPT ); Fri, 8 Sep 2017 11:36:26 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:34590 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932217AbdIHPgW (ORCPT ); Fri, 8 Sep 2017 11:36:22 -0400 Received: by mail-wm0-f66.google.com with SMTP id l19so1982886wmi.1; Fri, 08 Sep 2017 08:36:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=owFYxnK787Ud9TRMMs531N3In48svKrtFKwYj7nv/wc=; b=SYkaLzzzj42t5HwnrN5eSgC16ZyBITDEfWmxnYfpJYXZSyoBcKaZ5d34/7pCC4hkVz +dvB8S4lUzjTvaUjo28oZBqpr5A3Xg8hjojPadq+qaP/XcVYYkGxQzd8gHnLhXy2muId Sks6k6SyOTRP/kQKKcc8y2E8Si+F7QFjfB6Klr3knUG/jahcCY4wD6CBX9Di1kjihyxD OaKBH0rfAQmbyp+JJS4PJ4nq0ZyGj/rJxBZn8PWWiZJ3LNnIIJI/djy0YXofMCg+K8oE QF/4ez+ia9TwrFgPpkAE4EBE7GO1U/xH1BqMaAWiAqcc1UP/7geQ+AyTa+cRoWGGjsFC wvrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=owFYxnK787Ud9TRMMs531N3In48svKrtFKwYj7nv/wc=; b=T0jajso9ZrV9B+JELvFTGp9mVWlAIcETj2XqAbkYhH0LlgBccNj0EwlCQ1G7h/N4mK mJfZD3nj5r3ATL0/0t9BS9BXESkn8jFNToDS17OllYb19yqyFeXPpQfSZ4cvJCQ/z+IE e7p+Ur1R9broEVaHnCd8TKMtoWhaUcWjtfRgEzRbK9qiYHQUP4jt+OFj/w7FPnGLayhD b59yzJmOuXVPav8LHJ8UbgJNF9FiXYBolmxVykqL0FlwJKq0nBTsSf0rwfjqdAHigQly T/hkkkc1QfCnw/xuYDCmN5/YvQwjh89ky4tqIf7dweFnhncwEyxexxWfHsevr39ViMLC gxxQ== X-Gm-Message-State: AHPjjUj8ady311g09M/JfRWsbBvDtephaPB5EFmw6rnV51rxnvPaPKhZ N0DG9wYRZ+SKHg== X-Google-Smtp-Source: AOwi7QCmB90PGajvrxgyno2VImub4kajbKyF2GWBVPatSuwFadgLbD+aw60VWHb+Sa34/c73B1k9+g== X-Received: by 10.28.136.11 with SMTP id k11mr97555wmd.133.1504884980591; Fri, 08 Sep 2017 08:36:20 -0700 (PDT) Received: from localhost.localdomain (146.187.3.109.rev.sfr.net. [109.3.187.146]) by smtp.gmail.com with ESMTPSA id p199sm1689224wmb.28.2017.09.08.08.36.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Sep 2017 08:36:20 -0700 (PDT) From: Romain Izard To: Nicolas Ferre , Boris Brezillon , Michael Turquette , Stephen Boyd , Ludovic Desroches , Jonathan Cameron , Wenyou Yang , Josh Wu , David Woodhouse , Brian Norris , Marek Vasut , Cyrille Pitchen , Thierry Reding , Richard Genoud , Greg Kroah-Hartman , Alan Stern Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-mtd@lists.infradead.org, linux-pwm@vger.kernel.org, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Romain Izard Subject: [PATCH v1 04/10] mtd: nand: atmel: Avoid ECC errors when leaving backup mode Date: Fri, 8 Sep 2017 17:35:58 +0200 Message-Id: <20170908153604.28383-5-romain.izard.pro@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170908153604.28383-1-romain.izard.pro@gmail.com> References: <20170908153604.28383-1-romain.izard.pro@gmail.com> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org During backup mode, the contents of all registers will be cleared as the SoC will be completely powered down. For a product that boots on NAND Flash memory, the bootloader will obviously use the related controller to read the Flash and correct any detected error in the memory, before handling back control to the kernel's resuming entry point. In normal devices, it is up to the driver's suspend/resume code to restore the registers in a valid state. But the PMECC is not a regular device in the driver model when used with the legacy device tree binding for the Atmel NAND controller, and suspend/resume code is not called. As in my case the bootloader leaves the PMECC controller in a programmed state, and the controller is only reset at boot or after a NAND access, the first NAND Flash access with the Atmel controller will report uncorrectable ECC errors. To avoid this, systematically reset the PMECC controller before using it. Signed-off-by: Romain Izard --- drivers/mtd/nand/atmel/pmecc.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/nand/atmel/pmecc.c b/drivers/mtd/nand/atmel/pmecc.c index 8c210a5776bc..8d1208f38025 100644 --- a/drivers/mtd/nand/atmel/pmecc.c +++ b/drivers/mtd/nand/atmel/pmecc.c @@ -777,6 +777,9 @@ int atmel_pmecc_enable(struct atmel_pmecc_user *user, int op) mutex_lock(&user->pmecc->lock); + writel(PMECC_CTRL_RST, pmecc->regs.base + ATMEL_PMECC_CTRL); + writel(PMECC_CTRL_DISABLE, pmecc->regs.base + ATMEL_PMECC_CTRL); + cfg = user->cache.cfg; if (op == NAND_ECC_WRITE) cfg |= PMECC_CFG_WRITE_OP; @@ -797,10 +800,6 @@ EXPORT_SYMBOL_GPL(atmel_pmecc_enable); void atmel_pmecc_disable(struct atmel_pmecc_user *user) { - struct atmel_pmecc *pmecc = user->pmecc; - - writel(PMECC_CTRL_RST, pmecc->regs.base + ATMEL_PMECC_CTRL); - writel(PMECC_CTRL_DISABLE, pmecc->regs.base + ATMEL_PMECC_CTRL); mutex_unlock(&user->pmecc->lock); } EXPORT_SYMBOL_GPL(atmel_pmecc_disable); @@ -856,10 +855,6 @@ static struct atmel_pmecc *atmel_pmecc_create(struct platform_device *pdev, /* Disable all interrupts before registering the PMECC handler. */ writel(0xffffffff, pmecc->regs.base + ATMEL_PMECC_IDR); - /* Reset the ECC engine */ - writel(PMECC_CTRL_RST, pmecc->regs.base + ATMEL_PMECC_CTRL); - writel(PMECC_CTRL_DISABLE, pmecc->regs.base + ATMEL_PMECC_CTRL); - return pmecc; }