| Message ID | 20170908143344.12960-2-clg@kaod.org |
|---|---|
| State | New |
| Headers | show |
| Series | spapr: XIVE and CAS fixes | expand |
Shouldn't the patch title mention spapr instead of ppc/xive ? On Fri, 8 Sep 2017 16:33:42 +0200 Cédric Le Goater <clg@kaod.org> wrote: > On POWER9, the Client Architecture Support (CAS) negotiation process > determines whether the guest operates in XIVE Legacy compatibility or > in XIVE exploitation mode. Now that we have initial guest support for > the XIVE interrupt controller, let's fix the bits definition which have > evolved in the latest specs. > > The platform advertises the XIVE Exploitation Mode support using the > property "ibm,arch-vec-5-platform-support-vec-5", byte 23 bits 0-1 : > > - 0b00 XIVE legacy mode Only > - 0b01 XIVE exploitation mode Only > - 0b10 XIVE legacy or exploitation mode > > The OS asks for XIVE Exploitation Mode support using the property > "ibm,architecture-vec-5", byte 23 bits 0-1: > > - 0b00 XIVE legacy mode Only > - 0b01 XIVE exploitation mode Only > > Signed-off-by: Cédric Le Goater <clg@kaod.org> > --- > hw/ppc/spapr.c | 2 +- > include/hw/ppc/spapr_ovec.h | 3 ++- > 2 files changed, 3 insertions(+), 2 deletions(-) > > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c > index cec441cbf48d..3e3ff1fbc988 100644 > --- a/hw/ppc/spapr.c > +++ b/hw/ppc/spapr.c > @@ -914,7 +914,7 @@ static void spapr_dt_ov5_platform_support(void *fdt, int chosen) > PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); > > char val[2 * 4] = { > - 23, 0x00, /* Xive mode: 0 = legacy (as in ISA 2.7), 1 = Exploitation */ > + 23, 0x00, /* Xive mode, filled in below. */ > 24, 0x00, /* Hash/Radix, filled in below. */ > 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ > 26, 0x40, /* Radix options: GTSE == yes. */ > diff --git a/include/hw/ppc/spapr_ovec.h b/include/hw/ppc/spapr_ovec.h > index 9edfa5ff7530..bf25e5d954a1 100644 > --- a/include/hw/ppc/spapr_ovec.h > +++ b/include/hw/ppc/spapr_ovec.h > @@ -51,7 +51,8 @@ typedef struct sPAPROptionVector sPAPROptionVector; > #define OV5_FORM1_AFFINITY OV_BIT(5, 0) > #define OV5_HP_EVT OV_BIT(6, 5) > #define OV5_HPT_RESIZE OV_BIT(6, 7) > -#define OV5_XIVE_EXPLOIT OV_BIT(23, 7) > +#define OV5_XIVE_BOTH OV_BIT(23, 0) > +#define OV5_XIVE_EXPLOIT OV_BIT(23, 1) /* 1=exploitation 0=legacy */ > > /* ISA 3.00 MMU features: */ > #define OV5_MMU_BOTH OV_BIT(24, 0) /* Radix and hash */
On Fri, Sep 08, 2017 at 04:33:42PM +0200, Cédric Le Goater wrote: > On POWER9, the Client Architecture Support (CAS) negotiation process > determines whether the guest operates in XIVE Legacy compatibility or > in XIVE exploitation mode. Now that we have initial guest support for > the XIVE interrupt controller, let's fix the bits definition which have > evolved in the latest specs. > > The platform advertises the XIVE Exploitation Mode support using the > property "ibm,arch-vec-5-platform-support-vec-5", byte 23 bits 0-1 : > > - 0b00 XIVE legacy mode Only > - 0b01 XIVE exploitation mode Only > - 0b10 XIVE legacy or exploitation mode > > The OS asks for XIVE Exploitation Mode support using the property > "ibm,architecture-vec-5", byte 23 bits 0-1: > > - 0b00 XIVE legacy mode Only > - 0b01 XIVE exploitation mode Only > > Signed-off-by: Cédric Le Goater <clg@kaod.org> Applied to ppc-for-2.11, thanks. > --- > hw/ppc/spapr.c | 2 +- > include/hw/ppc/spapr_ovec.h | 3 ++- > 2 files changed, 3 insertions(+), 2 deletions(-) > > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c > index cec441cbf48d..3e3ff1fbc988 100644 > --- a/hw/ppc/spapr.c > +++ b/hw/ppc/spapr.c > @@ -914,7 +914,7 @@ static void spapr_dt_ov5_platform_support(void *fdt, int chosen) > PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); > > char val[2 * 4] = { > - 23, 0x00, /* Xive mode: 0 = legacy (as in ISA 2.7), 1 = Exploitation */ > + 23, 0x00, /* Xive mode, filled in below. */ > 24, 0x00, /* Hash/Radix, filled in below. */ > 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ > 26, 0x40, /* Radix options: GTSE == yes. */ > diff --git a/include/hw/ppc/spapr_ovec.h b/include/hw/ppc/spapr_ovec.h > index 9edfa5ff7530..bf25e5d954a1 100644 > --- a/include/hw/ppc/spapr_ovec.h > +++ b/include/hw/ppc/spapr_ovec.h > @@ -51,7 +51,8 @@ typedef struct sPAPROptionVector sPAPROptionVector; > #define OV5_FORM1_AFFINITY OV_BIT(5, 0) > #define OV5_HP_EVT OV_BIT(6, 5) > #define OV5_HPT_RESIZE OV_BIT(6, 7) > -#define OV5_XIVE_EXPLOIT OV_BIT(23, 7) > +#define OV5_XIVE_BOTH OV_BIT(23, 0) > +#define OV5_XIVE_EXPLOIT OV_BIT(23, 1) /* 1=exploitation 0=legacy */ > > /* ISA 3.00 MMU features: */ > #define OV5_MMU_BOTH OV_BIT(24, 0) /* Radix and hash */
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index cec441cbf48d..3e3ff1fbc988 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -914,7 +914,7 @@ static void spapr_dt_ov5_platform_support(void *fdt, int chosen) PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); char val[2 * 4] = { - 23, 0x00, /* Xive mode: 0 = legacy (as in ISA 2.7), 1 = Exploitation */ + 23, 0x00, /* Xive mode, filled in below. */ 24, 0x00, /* Hash/Radix, filled in below. */ 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 26, 0x40, /* Radix options: GTSE == yes. */ diff --git a/include/hw/ppc/spapr_ovec.h b/include/hw/ppc/spapr_ovec.h index 9edfa5ff7530..bf25e5d954a1 100644 --- a/include/hw/ppc/spapr_ovec.h +++ b/include/hw/ppc/spapr_ovec.h @@ -51,7 +51,8 @@ typedef struct sPAPROptionVector sPAPROptionVector; #define OV5_FORM1_AFFINITY OV_BIT(5, 0) #define OV5_HP_EVT OV_BIT(6, 5) #define OV5_HPT_RESIZE OV_BIT(6, 7) -#define OV5_XIVE_EXPLOIT OV_BIT(23, 7) +#define OV5_XIVE_BOTH OV_BIT(23, 0) +#define OV5_XIVE_EXPLOIT OV_BIT(23, 1) /* 1=exploitation 0=legacy */ /* ISA 3.00 MMU features: */ #define OV5_MMU_BOTH OV_BIT(24, 0) /* Radix and hash */
On POWER9, the Client Architecture Support (CAS) negotiation process determines whether the guest operates in XIVE Legacy compatibility or in XIVE exploitation mode. Now that we have initial guest support for the XIVE interrupt controller, let's fix the bits definition which have evolved in the latest specs. The platform advertises the XIVE Exploitation Mode support using the property "ibm,arch-vec-5-platform-support-vec-5", byte 23 bits 0-1 : - 0b00 XIVE legacy mode Only - 0b01 XIVE exploitation mode Only - 0b10 XIVE legacy or exploitation mode The OS asks for XIVE Exploitation Mode support using the property "ibm,architecture-vec-5", byte 23 bits 0-1: - 0b00 XIVE legacy mode Only - 0b01 XIVE exploitation mode Only Signed-off-by: Cédric Le Goater <clg@kaod.org> --- hw/ppc/spapr.c | 2 +- include/hw/ppc/spapr_ovec.h | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-)