From patchwork Mon Jan 31 15:20:43 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 81137 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B5B7FB6F10 for ; Tue, 1 Feb 2011 02:24:29 +1100 (EST) Received: from localhost ([127.0.0.1]:53690 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pjvc9-0007ld-98 for incoming@patchwork.ozlabs.org; Mon, 31 Jan 2011 10:24:25 -0500 Received: from [140.186.70.92] (port=48572 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PjvZC-0006T6-QM for qemu-devel@nongnu.org; Mon, 31 Jan 2011 10:21:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PjvZB-0001cF-KX for qemu-devel@nongnu.org; Mon, 31 Jan 2011 10:21:22 -0500 Received: from mail-bw0-f45.google.com ([209.85.214.45]:62056) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PjvZB-0001bM-DJ for qemu-devel@nongnu.org; Mon, 31 Jan 2011 10:21:21 -0500 Received: by mail-bw0-f45.google.com with SMTP id 16so5607723bwz.4 for ; Mon, 31 Jan 2011 07:21:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:subject:date:message-id:x-mailer :in-reply-to:references; bh=VykLtBkBdKkB0plYV4sMtF3+Yf16gPtj6/rhPQ/XHK8=; b=F1HmIrc7qkKfRUcdBY7a4KIAlz/HwNNj9gyS8rsLVVeAB1GlGx37vR8I0+bNWtssZh ylhKV3taItij/+BBg/Q21ZuvDNHK0DCpvLMp3XQ3JR9s/2jgObOpjycVnpj5+rBwU+Zs WWbX5NGob6Zaui12Ua8yHKubYnCxox4h1YsoU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:subject:date:message-id:x-mailer:in-reply-to:references; b=RAI4Vfc55u1Y2F8Eu6pFbFIxDGMo5E6Ue/NmZhlivyz42L2s5FzacXyolKvIdEFm59 EGC0mvCYnaJIlwQIIl1bEvr3hGEa6CKDB1TakOxOjIReDnPqp1qkWwreJtYyge1D66id hhyPj6hn2UFULzWqf56uKsfBrNkAwiJp00wQY= Received: by 10.204.59.16 with SMTP id j16mr5439865bkh.138.1296487280961; Mon, 31 Jan 2011 07:21:20 -0800 (PST) Received: from doriath.ww600.siemens.net ([91.213.169.4]) by mx.google.com with ESMTPS id z18sm8098299bkf.20.2011.01.31.07.21.19 (version=SSLv3 cipher=RC4-MD5); Mon, 31 Jan 2011 07:21:20 -0800 (PST) From: Dmitry Eremin-Solenikov To: qemu-devel@nongnu.org Date: Mon, 31 Jan 2011 18:20:43 +0300 Message-Id: <1296487250-28254-4-git-send-email-dbaryshkov@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1296487250-28254-1-git-send-email-dbaryshkov@gmail.com> References: <1296487250-28254-1-git-send-email-dbaryshkov@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.214.45 Subject: [Qemu-devel] [PATCH 04/11] arm-pic: add one extra interrupt to support EXITTB interrupts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Some ARM processors (consider PXA2xx, Omap1, etc.) want to be able to send CPU_INTERRUPT_EXITTB to the cpu. Support doing that through common arm_pic. Signed-off-by: Dmitry Eremin-Solenikov --- hw/arm-misc.h | 1 + hw/arm_pic.c | 6 +++++- 2 files changed, 6 insertions(+), 1 deletions(-) diff --git a/hw/arm-misc.h b/hw/arm-misc.h index 010acb4..f2e45ee 100644 --- a/hw/arm-misc.h +++ b/hw/arm-misc.h @@ -14,6 +14,7 @@ /* The CPU is also modeled as an interrupt controller. */ #define ARM_PIC_CPU_IRQ 0 #define ARM_PIC_CPU_FIQ 1 +#define ARM_PIC_CPU_WAKE 2 qemu_irq *arm_pic_init_cpu(CPUState *env); /* armv7m.c */ diff --git a/hw/arm_pic.c b/hw/arm_pic.c index f44568c..bd5ce55 100644 --- a/hw/arm_pic.c +++ b/hw/arm_pic.c @@ -38,6 +38,10 @@ static void arm_pic_cpu_handler(void *opaque, int irq, int level) else cpu_reset_interrupt(env, CPU_INTERRUPT_FIQ); break; + case ARM_PIC_CPU_WAKE: + if (env->halted && level) + cpu_interrupt(env, CPU_INTERRUPT_EXITTB); + break; default: hw_error("arm_pic_cpu_handler: Bad interrput line %d\n", irq); } @@ -45,5 +49,5 @@ static void arm_pic_cpu_handler(void *opaque, int irq, int level) qemu_irq *arm_pic_init_cpu(CPUState *env) { - return qemu_allocate_irqs(arm_pic_cpu_handler, env, 2); + return qemu_allocate_irqs(arm_pic_cpu_handler, env, 3); }