From patchwork Thu Sep 7 11:54:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shilpasri G Bhat X-Patchwork-Id: 810993 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xnzRF6QNhz9sRV for ; Thu, 7 Sep 2017 21:55:21 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xnzRF4zhSzDrXP for ; Thu, 7 Sep 2017 21:55:21 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=shilpa.bhat@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xnzR04ZfDzDrWM for ; Thu, 7 Sep 2017 21:55:07 +1000 (AEST) Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v87Bt2J7089493 for ; Thu, 7 Sep 2017 07:55:05 -0400 Received: from e23smtp07.au.ibm.com (e23smtp07.au.ibm.com [202.81.31.140]) by mx0a-001b2d01.pphosted.com with ESMTP id 2cu1p0bv0r-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 07 Sep 2017 07:55:04 -0400 Received: from localhost by e23smtp07.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 7 Sep 2017 21:55:00 +1000 Received: from d23av04.au.ibm.com (d23av04.au.ibm.com [9.190.235.139]) by d23relay06.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v87Bt04842336334 for ; Thu, 7 Sep 2017 21:55:00 +1000 Received: from d23av04.au.ibm.com (localhost [127.0.0.1]) by d23av04.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v87Bt1Xp016489 for ; Thu, 7 Sep 2017 21:55:01 +1000 Received: from oc4502181600.ibm.com ([9.195.47.48]) by d23av04.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v87BsvY7016214; Thu, 7 Sep 2017 21:54:58 +1000 From: Shilpasri G Bhat To: skiboot@lists.ozlabs.org Date: Thu, 7 Sep 2017 17:24:52 +0530 X-Mailer: git-send-email 1.8.3.1 X-TM-AS-MML: disable x-cbid: 17090711-0044-0000-0000-000002862BDC X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17090711-0045-0000-0000-0000071B2EC9 Message-Id: <1504785292-11222-1-git-send-email-shilpa.bhat@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-09-07_08:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1709070176 Subject: [Skiboot] [PATCH V2] opal-prd: Add support for runtime OCC reset in ZZ X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ego@linux.vnet.ibm.com MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This patch handles OCC_RESET runtime events in host opal-prd and also provides support for calling 'hostinterface->wakeup()' which is required for doing the reset operation. Signed-off-by: Shilpasri G Bhat --- Changes from V2: - Disable hservice_wakeup() on BMC - Check the status and send a single FSP message core/hostservices.c | 28 +++++++++++++++-------- external/opal-prd/opal-prd.c | 54 +++++++++++++++++++++++++++++++++++++++++++- external/opal-prd/thunk.S | 2 +- hw/occ.c | 47 +++++++++++++++++++++++++++++++++++++- hw/prd.c | 8 +++++++ include/opal-api.h | 10 ++++++++ include/skiboot.h | 2 ++ 7 files changed, 139 insertions(+), 12 deletions(-) diff --git a/core/hostservices.c b/core/hostservices.c index 345c8c0..799b483 100644 --- a/core/hostservices.c +++ b/core/hostservices.c @@ -721,17 +721,23 @@ static int hservice_wakeup(uint32_t i_core, uint32_t i_mode) struct cpu_thread *cpu; int rc = OPAL_SUCCESS; - /* - * Mask out the top nibble of i_core since it may contain - * 0x4 (which we use for XSCOM targeting) - */ - i_core &= 0x0fffffff; + switch (proc_gen) { + case proc_gen_p8: + i_core &= SPR_PIR_P8_MASK; + i_core <<= 3; + break; + case proc_gen_p9: + i_core &= SPR_PIR_P9_MASK; + i_core <<= 2; + break; + default: + return OPAL_UNSUPPORTED; + } /* What do we need to do ? */ switch(i_mode) { case 0: /* Assert special wakeup */ - /* XXX Assume P8 */ - cpu = find_cpu_by_pir(i_core << 3); + cpu = find_cpu_by_pir(i_core); if (!cpu) return OPAL_PARAMETER; prlog(PR_DEBUG, "HBRT: Special wakeup assert for core 0x%x," @@ -742,8 +748,7 @@ static int hservice_wakeup(uint32_t i_core, uint32_t i_mode) cpu->hbrt_spec_wakeup++; return rc; case 1: /* Deassert special wakeup */ - /* XXX Assume P8 */ - cpu = find_cpu_by_pir(i_core << 3); + cpu = find_cpu_by_pir(i_core); if (!cpu) return OPAL_PARAMETER; prlog(PR_DEBUG, "HBRT: Special wakeup release for core" @@ -774,6 +779,11 @@ static int hservice_wakeup(uint32_t i_core, uint32_t i_mode) } } +int core_special_wakeup(u32 core, u32 mode) +{ + return hservice_wakeup(core, mode); +} + static struct host_interfaces hinterface = { .interface_version = HOSTBOOT_RUNTIME_INTERFACE_VERSION, .puts = hservice_puts, diff --git a/external/opal-prd/opal-prd.c b/external/opal-prd/opal-prd.c index a09a636..8af523e 100644 --- a/external/opal-prd/opal-prd.c +++ b/external/opal-prd/opal-prd.c @@ -506,6 +506,25 @@ int hservice_i2c_write(uint64_t i_master, uint16_t i_devAddr, i_offset, i_length, i_data); } +int hservice_wakeup(u32 core, u32 mode) +{ + int rc; + struct opal_prd_msg msg; + + msg.hdr.type = OPAL_PRD_MSG_TYPE_CORE_SPECIAL_WAKEUP; + msg.hdr.size = htobe16(sizeof(msg)); + msg.spl_wakeup.core = htobe32(core); + msg.spl_wakeup.mode = htobe32(mode); + + rc = write(ctx->fd, &msg, sizeof(msg)); + if (rc != sizeof(msg)) { + pr_log(LOG_ERR, "FW: failed for core %x : %m\n", core); + return rc; + } + + return 0; +} + static void ipmi_init(struct opal_prd_ctx *ctx) { insert_module("ipmi_devintf"); @@ -1353,9 +1372,24 @@ static int pm_complex_reset(uint64_t chip) return rc; } +static bool is_fsp(void) +{ + char *path; + int rc; + + rc = asprintf(&path, "%s/fsps", devicetree_base); + if (rc < 0) { + pr_log(LOG_ERR, "PRD: error creating '/fsps' path %m"); + return false; + } + + return access(path, F_OK) ? false : true; +} + static int handle_msg_occ_reset(struct opal_prd_ctx *ctx, struct opal_prd_msg *msg) { + struct opal_prd_msg omsg; uint32_t proc; int rc; @@ -1365,7 +1399,22 @@ static int handle_msg_occ_reset(struct opal_prd_ctx *ctx, rc = pm_complex_reset(proc); - return rc; + if (!is_fsp()) + return rc; + + /* Send only for zz */ + omsg.hdr.type = OPAL_PRD_MSG_TYPE_OCC_RESET_STATUS; + omsg.hdr.size = htobe16(sizeof(omsg)); + omsg.occ_reset_status.chip = htobe64(proc); + omsg.occ_reset_status.status = htobe64(rc); + + rc = write(ctx->fd, &omsg, sizeof(omsg)); + if (rc != sizeof(omsg)) { + pr_log(LOG_ERR, "FW: Failed to send OCC_RESET status message: %m"); + return rc; + } + + return 0; } static int handle_msg_firmware_notify(struct opal_prd_ctx *ctx, @@ -1961,6 +2010,9 @@ static int run_prd_daemon(struct opal_prd_ctx *ctx) hinterface.pnor_write = NULL; } + if (!is_fsp()) + hinterface.wakeup = NULL; + ipmi_init(ctx); pr_debug("HBRT: calling hservices_init"); diff --git a/external/opal-prd/thunk.S b/external/opal-prd/thunk.S index cca5890..ee3d7c3 100644 --- a/external/opal-prd/thunk.S +++ b/external/opal-prd/thunk.S @@ -183,7 +183,7 @@ hinterface: DISABLED_THUNK(hservice_lid_load) DISABLED_THUNK(hservice_lid_unload) CALLBACK_THUNK(hservice_get_reserved_mem) - DISABLED_THUNK(hservice_wakeup) + CALLBACK_THUNK(hservice_wakeup) CALLBACK_THUNK(hservice_nanosleep) DISABLED_THUNK(hservice_report_occ_failure) CALLBACK_THUNK(hservice_clock_gettime) diff --git a/hw/occ.c b/hw/occ.c index 78c6a6a..e6f0998 100644 --- a/hw/occ.c +++ b/hw/occ.c @@ -1837,6 +1837,40 @@ out: return rc; } +static u32 last_seq_id; + +int fsp_occ_reset_status(u64 chipid, s64 status) +{ + struct fsp_msg *stat; + int rc = OPAL_NO_MEM; + int status_word = 0; + + if (status) { + struct proc_chip *chip = get_chip(chipid); + + if (!chip) + return OPAL_PARAMETER; + + status_word = 0xfe00 | (chip->pcid & 0xff); + log_simple_error(&e_info(OPAL_RC_OCC_RESET), + "OCC: Error %d in OCC reset of chip %lld\n", rc, + chipid); + } + + stat = fsp_mkmsg(FSP_CMD_RESET_OCC_STAT, 2, status_word, last_seq_id); + if (!stat) + return rc; + + rc = fsp_queue_msg(stat, fsp_freemsg); + if (rc) { + fsp_freemsg(stat); + log_simple_error(&e_info(OPAL_RC_OCC_RESET), + "OCC: Error %d queueing FSP OCC RESET STATUS message\n", + rc); + } + return rc; +} + static void occ_do_reset(u8 scope, u32 dbob_id, u32 seq_id) { struct fsp_msg *rsp, *stat; @@ -1877,7 +1911,18 @@ static void occ_do_reset(u8 scope, u32 dbob_id, u32 seq_id) * FSP will request OCC to left in stopped state. */ - rc = host_services_occ_stop(); + switch (proc_gen) { + case proc_gen_p8: + rc = host_services_occ_stop(); + break; + case proc_gen_p9: + last_seq_id = seq_id; + for_each_chip(chip) + prd_occ_reset(chip->id); + return; + default: + return; + } /* Handle fallback to preload */ if (rc == -ENOENT && chip->homer_base) { diff --git a/hw/prd.c b/hw/prd.c index d076c19..dcda9c8 100644 --- a/hw/prd.c +++ b/hw/prd.c @@ -418,6 +418,14 @@ static int64_t opal_prd_msg(struct opal_prd_msg *msg) case OPAL_PRD_MSG_TYPE_FIRMWARE_REQUEST: rc = prd_msg_handle_firmware_req(msg); break; + case OPAL_PRD_MSG_TYPE_OCC_RESET_STATUS: + rc = fsp_occ_reset_status(msg->occ_reset_status.chip, + msg->occ_reset_status.status); + break; + case OPAL_PRD_MSG_TYPE_CORE_SPECIAL_WAKEUP: + rc = core_special_wakeup(msg->spl_wakeup.core, + msg->spl_wakeup.mode); + break; default: rc = OPAL_UNSUPPORTED; } diff --git a/include/opal-api.h b/include/opal-api.h index 0ff0db0..2f303f9 100644 --- a/include/opal-api.h +++ b/include/opal-api.h @@ -1052,6 +1052,8 @@ enum opal_prd_msg_type { OPAL_PRD_MSG_TYPE_FIRMWARE_RESPONSE, /* HBRT <-- OPAL */ OPAL_PRD_MSG_TYPE_FIRMWARE_NOTIFY, /* HBRT <-- OPAL */ OPAL_PRD_MSG_TYPE_SBE_PASSTHROUGH, /* HBRT <-- OPAL */ + OPAL_PRD_MSG_TYPE_OCC_RESET_STATUS, /* HBRT --> OPAL */ + OPAL_PRD_MSG_TYPE_CORE_SPECIAL_WAKEUP, /* HBRT --> OPAL */ }; struct opal_prd_msg_header { @@ -1099,6 +1101,14 @@ struct opal_prd_msg { struct { __be64 chip; } sbe_passthrough; + struct { + __be64 chip; + __be64 status; /* 0 SUCCESS */ + } occ_reset_status; + struct { + __be32 core; + __be32 mode; + } spl_wakeup; }; }; diff --git a/include/skiboot.h b/include/skiboot.h index 0ab9f38..3ec822e 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -320,4 +320,6 @@ extern int occ_sensor_group_clear(u32 group_hndl, int token); extern void occ_add_sensor_groups(struct dt_node *sg, u32 *phandles, int nr_phandles, int chipid); +extern int fsp_occ_reset_status(u64 chipid, s64 status); +extern int core_special_wakeup(u32 core, u32 mode); #endif /* __SKIBOOT_H */