From patchwork Mon Jan 31 00:30:41 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 81060 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 6DBF9B70E3 for ; Mon, 31 Jan 2011 11:43:25 +1100 (EST) Received: from localhost ([127.0.0.1]:55545 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PjhrW-0000Ez-2O for incoming@patchwork.ozlabs.org; Sun, 30 Jan 2011 19:43:22 -0500 Received: from [140.186.70.92] (port=36139 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pjhfv-0002Pg-29 for qemu-devel@nongnu.org; Sun, 30 Jan 2011 19:31:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Pjhfs-0004Jw-FJ for qemu-devel@nongnu.org; Sun, 30 Jan 2011 19:31:22 -0500 Received: from mail.serverraum.org ([78.47.150.89]:47267) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Pjhfs-0004Jf-4n for qemu-devel@nongnu.org; Sun, 30 Jan 2011 19:31:20 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.serverraum.org (Postfix) with ESMTP id 914233EEEE; Mon, 31 Jan 2011 01:31:19 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at mail.serverraum.org Received: from mail.serverraum.org ([127.0.0.1]) by localhost (web.serverraum.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id b6GvKG9r8HNx; Mon, 31 Jan 2011 01:31:19 +0100 (CET) Received: from thanatos.fritz.box (77-22-60-162-dynip.superkabel.de [77.22.60.162]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.serverraum.org (Postfix) with ESMTPSA id 1F1AC3EEED; Mon, 31 Jan 2011 01:31:19 +0100 (CET) From: Michael Walle To: qemu-devel@nongnu.org Date: Mon, 31 Jan 2011 01:30:41 +0100 Message-Id: <1296433846-18097-13-git-send-email-michael@walle.cc> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1296433846-18097-1-git-send-email-michael@walle.cc> References: <1296433846-18097-1-git-send-email-michael@walle.cc> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 78.47.150.89 Cc: "Edgar E. Iglesias" , Michael Walle , Alexander Graf Subject: [Qemu-devel] [PATCH 12/17] lm32: support for creating device tree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds helper functions to create a ROM, which contains a hardware description of a board. This is used in Theobromas LM32 Linux port. Signed-off-by: Michael Walle --- hw/lm32_hwsetup.h | 172 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 172 insertions(+), 0 deletions(-) create mode 100644 hw/lm32_hwsetup.h diff --git a/hw/lm32_hwsetup.h b/hw/lm32_hwsetup.h new file mode 100644 index 0000000..c7d4e05 --- /dev/null +++ b/hw/lm32_hwsetup.h @@ -0,0 +1,172 @@ +/* + * LatticeMico32 hwsetup helper functions. + * + * Copyright (c) 2010 Michael Walle + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +/* + * These are helper functions for creating the hardware description blob used + * in the Theobroma's uClinux port. + */ + +#include "qemu-common.h" +#include "loader.h" + +struct hwsetup { + void *data; + void *ptr; +}; + +enum hwsetup_tag { + HWSETUP_TAG_EOL = 0, + HWSETUP_TAG_CPU = 1, + HWSETUP_TAG_ASRAM = 2, + HWSETUP_TAG_FLASH = 3, + HWSETUP_TAG_SDRAM = 4, + HWSETUP_TAG_OCM = 5, + HWSETUP_TAG_DDR_SDRAM = 6, + HWSETUP_TAG_DDR2_SDRAM = 7, + HWSETUP_TAG_TIMER = 8, + HWSETUP_TAG_UART = 9, + HWSETUP_TAG_GPIO = 10, + HWSETUP_TAG_TRISPEEDMAC = 11, + HWSETUP_TAG_I2CM = 12, + HWSETUP_TAG_LEDS = 13, + HWSETUP_TAG_7SEG = 14, + HWSETUP_TAG_SPI_S = 15, + HWSETUP_TAG_SPI_M = 16, +}; + +static inline struct hwsetup *hwsetup_init(void) +{ + struct hwsetup *hw; + + hw = qemu_malloc(sizeof(struct hwsetup)); + hw->data = qemu_mallocz(TARGET_PAGE_SIZE); + hw->ptr = hw->data; + + return hw; +} + +static inline void hwsetup_free(struct hwsetup *hw) +{ + qemu_free(hw->data); + qemu_free(hw); +} + +static inline void hwsetup_create_rom(struct hwsetup *hw, ram_addr_t base) +{ + rom_add_blob("hwsetup", hw->data, TARGET_PAGE_SIZE, base); +} + +static inline void hwsetup_add_u8(struct hwsetup *hw, uint8_t u) +{ + stb_p(hw->ptr, u); + hw->ptr += 1; +} + +static inline void hwsetup_add_u32(struct hwsetup *hw, uint32_t u) +{ + stl_p(hw->ptr, u); + hw->ptr += 4; +} + +static inline void hwsetup_add_tag(struct hwsetup *hw, enum hwsetup_tag t) +{ + stl_p(hw->ptr, t); + hw->ptr += 4; +} + +static inline void hwsetup_add_str(struct hwsetup *hw, const char *str) +{ + strncpy(hw->ptr, str, 31); /* make sure last byte is zero */ + hw->ptr += 32; +} + +static inline void hwsetup_add_trailer(struct hwsetup *hw) +{ + hwsetup_add_u32(hw, 8); /* size */ + hwsetup_add_tag(hw, HWSETUP_TAG_EOL); +} + +static inline void hwsetup_add_cpu(struct hwsetup *hw, + const char *name, uint32_t frequency) +{ + hwsetup_add_u32(hw, 44); /* size */ + hwsetup_add_tag(hw, HWSETUP_TAG_CPU); + hwsetup_add_str(hw, name); + hwsetup_add_u32(hw, frequency); +} + +static inline void hwsetup_add_flash(struct hwsetup *hw, + const char *name, uint32_t base, uint32_t size) +{ + hwsetup_add_u32(hw, 52); /* size */ + hwsetup_add_tag(hw, HWSETUP_TAG_FLASH); + hwsetup_add_str(hw, name); + hwsetup_add_u32(hw, base); + hwsetup_add_u32(hw, size); + hwsetup_add_u8(hw, 8); /* read latency */ + hwsetup_add_u8(hw, 8); /* write latency */ + hwsetup_add_u8(hw, 25); /* address width */ + hwsetup_add_u8(hw, 32); /* data width */ +} + +static inline void hwsetup_add_ddr_sdram(struct hwsetup *hw, + const char *name, uint32_t base, uint32_t size) +{ + hwsetup_add_u32(hw, 48); /* size */ + hwsetup_add_tag(hw, HWSETUP_TAG_DDR_SDRAM); + hwsetup_add_str(hw, name); + hwsetup_add_u32(hw, base); + hwsetup_add_u32(hw, size); +} + +static inline void hwsetup_add_timer(struct hwsetup *hw, + const char *name, uint32_t base, uint32_t irq) +{ + hwsetup_add_u32(hw, 56); /* size */ + hwsetup_add_tag(hw, HWSETUP_TAG_TIMER); + hwsetup_add_str(hw, name); + hwsetup_add_u32(hw, base); + hwsetup_add_u8(hw, 1); /* wr_tickcount */ + hwsetup_add_u8(hw, 1); /* rd_tickcount */ + hwsetup_add_u8(hw, 1); /* start_stop_control */ + hwsetup_add_u8(hw, 32); /* counter_width */ + hwsetup_add_u32(hw, 20); /* reload_ticks */ + hwsetup_add_u8(hw, irq); + hwsetup_add_u8(hw, 0); /* padding */ + hwsetup_add_u8(hw, 0); /* padding */ + hwsetup_add_u8(hw, 0); /* padding */ +} + +static inline void hwsetup_add_uart(struct hwsetup *hw, + const char *name, uint32_t base, uint32_t irq) +{ + hwsetup_add_u32(hw, 56); /* size */ + hwsetup_add_tag(hw, HWSETUP_TAG_UART); + hwsetup_add_str(hw, name); + hwsetup_add_u32(hw, base); + hwsetup_add_u32(hw, 115200); /* baudrate */ + hwsetup_add_u8(hw, 8); /* databits */ + hwsetup_add_u8(hw, 1); /* stopbits */ + hwsetup_add_u8(hw, 1); /* use_interrupt */ + hwsetup_add_u8(hw, 1); /* block_on_transmit */ + hwsetup_add_u8(hw, 1); /* block_on_receive */ + hwsetup_add_u8(hw, 4); /* rx_buffer_size */ + hwsetup_add_u8(hw, 4); /* tx_buffer_size */ + hwsetup_add_u8(hw, irq); +}