From patchwork Mon Jan 31 00:30:38 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 81056 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8BB30B70E3 for ; Mon, 31 Jan 2011 11:40:42 +1100 (EST) Received: from localhost ([127.0.0.1]:35177 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pjhld-0005Gm-FT for incoming@patchwork.ozlabs.org; Sun, 30 Jan 2011 19:37:17 -0500 Received: from [140.186.70.92] (port=36114 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pjhft-0002Ow-Ul for qemu-devel@nongnu.org; Sun, 30 Jan 2011 19:31:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Pjhfq-0004JG-VD for qemu-devel@nongnu.org; Sun, 30 Jan 2011 19:31:21 -0500 Received: from mail.serverraum.org ([78.47.150.89]:58611) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Pjhfq-0004J1-MQ for qemu-devel@nongnu.org; Sun, 30 Jan 2011 19:31:18 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.serverraum.org (Postfix) with ESMTP id 0C01B3EED0; Mon, 31 Jan 2011 01:31:18 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at mail.serverraum.org Received: from mail.serverraum.org ([127.0.0.1]) by localhost (web.serverraum.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id T5NSaW88LiFs; Mon, 31 Jan 2011 01:31:17 +0100 (CET) Received: from thanatos.fritz.box (77-22-60-162-dynip.superkabel.de [77.22.60.162]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.serverraum.org (Postfix) with ESMTPSA id 8C16F3EEF0; Mon, 31 Jan 2011 01:31:17 +0100 (CET) From: Michael Walle To: qemu-devel@nongnu.org Date: Mon, 31 Jan 2011 01:30:38 +0100 Message-Id: <1296433846-18097-10-git-send-email-michael@walle.cc> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1296433846-18097-1-git-send-email-michael@walle.cc> References: <1296433846-18097-1-git-send-email-michael@walle.cc> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 78.47.150.89 Cc: "Edgar E. Iglesias" , Michael Walle , Alexander Graf Subject: [Qemu-devel] [PATCH 09/17] lm32: timer model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds support for the LatticeMico32 system timer. Signed-off-by: Michael Walle --- Makefile.target | 1 + hw/lm32_timer.c | 227 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ trace-events | 6 ++ 3 files changed, 234 insertions(+), 0 deletions(-) create mode 100644 hw/lm32_timer.c diff --git a/Makefile.target b/Makefile.target index c9a61a0..04c4214 100644 --- a/Makefile.target +++ b/Makefile.target @@ -251,6 +251,7 @@ obj-ppc-y += xilinx_ethlite.o obj-lm32-y += lm32_pic.o obj-lm32-y += lm32_pic_cpu.o obj-lm32-y += lm32_juart.o +obj-lm32-y += lm32_timer.o obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o obj-mips-y += mips_addr.o mips_timer.o mips_int.o diff --git a/hw/lm32_timer.c b/hw/lm32_timer.c new file mode 100644 index 0000000..3bfc29d --- /dev/null +++ b/hw/lm32_timer.c @@ -0,0 +1,227 @@ +/* + * QEMU model of the LatticeMico32 timer block. + * + * Copyright (c) 2010 Michael Walle + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + * + * Specification available at: + * http://www.latticesemi.com/documents/mico32timer.pdf + */ + +#include "hw.h" +#include "sysbus.h" +#include "trace.h" +#include "qemu-timer.h" + +#define DEFAULT_FREQUENCY (50*1000000) + +enum { + R_SR = 0, + R_CR, + R_PERIOD, + R_SNAPSHOT, + R_MAX +}; + +enum { + SR_TO = (1 << 0), + SR_RUN = (1 << 1), +}; + +enum { + CR_ITO = (1 << 0), + CR_CONT = (1 << 1), + CR_START = (1 << 2), + CR_STOP = (1 << 3), +}; + +struct LM32TimerState { + SysBusDevice busdev; + + QEMUBH *bh; + ptimer_state *ptimer; + + qemu_irq irq; + uint32_t freq_hz; + + uint32_t regs[R_MAX]; +}; +typedef struct LM32TimerState LM32TimerState; + +static void timer_update_irq(LM32TimerState *s) +{ + int state = s->regs[R_SR] & SR_TO && s->regs[R_CR] & CR_ITO; + + trace_lm32_timer_irq_state(state); + qemu_set_irq(s->irq, state); +} + +static uint32_t timer_read(void *opaque, target_phys_addr_t addr) +{ + LM32TimerState *s = opaque; + uint32_t r = 0; + + addr >>= 2; + switch (addr) { + case R_SR: + case R_CR: + case R_PERIOD: + r = s->regs[addr]; + break; + case R_SNAPSHOT: + r = (uint32_t)ptimer_get_count(s->ptimer); + break; + + default: + hw_error("lm32_timer: read access to unkown register 0x" + TARGET_FMT_plx, addr << 2); + break; + + } + + trace_lm32_timer_memory_read(addr << 2, r); + return r; +} + +static void timer_write(void *opaque, target_phys_addr_t addr, uint32_t value) +{ + LM32TimerState *s = opaque; + + trace_lm32_timer_memory_write(addr, value); + + addr >>= 2; + switch (addr) { + case R_SR: + s->regs[R_SR] &= ~SR_TO; + break; + case R_CR: + s->regs[R_CR] = value; + if (s->regs[R_CR] & CR_START) { + ptimer_run(s->ptimer, 1); + } + if (s->regs[R_CR] & CR_STOP) { + ptimer_stop(s->ptimer); + } + break; + case R_PERIOD: + s->regs[R_PERIOD] = value; + ptimer_set_count(s->ptimer, value); + break; + case R_SNAPSHOT: + hw_error("lm32_timer: write access to read only register 0x" + TARGET_FMT_plx, addr << 2); + break; + + default: + hw_error("lm32_timer: write access to unkown register 0x" + TARGET_FMT_plx, addr << 2); + break; + } + timer_update_irq(s); +} + +static CPUReadMemoryFunc * const timer_read_fn[] = { + NULL, + NULL, + &timer_read, +}; + +static CPUWriteMemoryFunc * const timer_write_fn[] = { + NULL, + NULL, + &timer_write, +}; + +static void timer_hit(void *opaque) +{ + LM32TimerState *s = opaque; + + trace_lm32_timer_hit(); + + s->regs[R_SR] |= SR_TO; + + if (s->regs[R_CR] & CR_CONT) { + ptimer_set_count(s->ptimer, s->regs[R_PERIOD]); + ptimer_run(s->ptimer, 1); + } + + timer_update_irq(s); +} + +static void timer_reset(void *opaque) +{ + LM32TimerState *s = opaque; + int i; + + for (i = 0; i < R_MAX; i++) { + s->regs[i] = 0; + } + ptimer_stop(s->ptimer); + qemu_irq_lower(s->irq); +} + +static int lm32_timer_init(SysBusDevice *dev) +{ + LM32TimerState *s = FROM_SYSBUS(typeof(*s), dev); + int timer_regs; + + sysbus_init_irq(dev, &s->irq); + + s->bh = qemu_bh_new(timer_hit, s); + s->ptimer = ptimer_init(s->bh); + ptimer_set_freq(s->ptimer, s->freq_hz); + + timer_regs = cpu_register_io_memory(timer_read_fn, timer_write_fn, s, + DEVICE_NATIVE_ENDIAN); + sysbus_init_mmio(dev, R_MAX * 4, timer_regs); + + qemu_register_reset(timer_reset, s); + + return 0; +} + +static const VMStateDescription vmstate_lm32_timer = { + .name = "lm32-timer", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_PTIMER(ptimer, LM32TimerState), + VMSTATE_UINT32(freq_hz, LM32TimerState), + VMSTATE_UINT32_ARRAY(regs, LM32TimerState, R_MAX), + VMSTATE_END_OF_LIST() + } +}; + +static SysBusDeviceInfo lm32_timer_info = { + .init = lm32_timer_init, + .qdev.name = "lm32-timer", + .qdev.size = sizeof(LM32TimerState), + .qdev.vmsd = &vmstate_lm32_timer, + .qdev.props = (Property[]) { + DEFINE_PROP_UINT32( + "frequency", LM32TimerState, freq_hz, DEFAULT_FREQUENCY + ), + DEFINE_PROP_END_OF_LIST(), + } +}; + +static void lm32_timer_register(void) +{ + sysbus_register_withprop(&lm32_timer_info); +} + +device_init(lm32_timer_register) diff --git a/trace-events b/trace-events index c82588f..357c5f7 100644 --- a/trace-events +++ b/trace-events @@ -228,3 +228,9 @@ disable lm32_juart_get_jtx(uint32_t value) "value=%08x" disable lm32_juart_set_jtx(uint32_t value) "value=%08x" disable lm32_juart_get_jrx(uint32_t value) "value=%08x" disable lm32_juart_set_jrx(uint32_t value) "value=%08x" + +# hw/lm32_timer.c +disable lm32_timer_memory_write(uint32_t addr, uint32_t value) "addr=%08x value=%08x" +disable lm32_timer_memory_read(uint32_t addr, uint32_t value) "addr=%08x value=%08x" +disable lm32_timer_hit(void) "Timer hit" +disable lm32_timer_irq_state(int level) "Timer IRQ state %d"