Message ID | 20170904104655.29103-9-ran.wang_1@nxp.com |
---|---|
State | Accepted |
Delegated to: | York Sun |
Headers | show |
Series | [U-Boot,v5,1/9] armv8: Add scfg_clrsetbits_32(), scfg_clrbits_32() | expand |
On 09/04/2017 04:04 AM, Ran Wang wrote: > Rx Compliance tests may fail intermittently at high > jitter frequencies using default register values > > Program register USB_PHY_RX_OVRD_IN_HI in certain sequence > to make the Rx compliance test pass. > > Signed-off-by: Sriram Dash <sriram.dash@nxp.com> > Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> > Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com> > Signed-off-by: Ran Wang <ran.wang_1@nxp.com> > --- > Change in v5: > - none > > Change in v4: > Update commit message about register setting. > > Change in v3: > - none > > Change in v2: > In function erratum_a009007(): > 1.Put a blank line after variable declaration. > Reordered Kconfig options. Applied to fsl-qoriq master. Thanks. York
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index ee09dd6fed..a77bb06cf9 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -8,6 +8,7 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A008997 + select SYS_FSL_ERRATUM_A009007 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR_BE if SYS_FSL_DDR @@ -70,6 +71,11 @@ config SYS_FSL_ERRATUM_A008997 help Workaround for USB PHY erratum A008997 +config SYS_FSL_ERRATUM_A009007 + bool + help + Workaround for USB PHY erratum A009007 + config SYS_FSL_SRDS_1 bool diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index f409ad7f44..57c6f3e53c 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -92,6 +92,17 @@ static void erratum_a008997(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ } +static void erratum_a009007(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009007 + void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE; + + out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); + out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); + out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); + out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4); +#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */ +} void s_init(void) { @@ -183,6 +194,7 @@ int arch_soc_init(void) erratum_a009008(); erratum_a009798(); erratum_a008997(); + erratum_a009007(); return 0; } diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index e5c06170da..157643eb91 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -181,6 +181,13 @@ struct ccsr_gur { #define SCFG_USB_PCSTXSWINGFULL_MASK 0x0000FE00 #define SCFG_USB_PCSTXSWINGFULL_VAL 0x00008E00 +#define USB_PHY_BASE 0x08510000 +#define USB_PHY_RX_OVRD_IN_HI 0x200c +#define USB_PHY_RX_EQ_VAL_1 0x0000 +#define USB_PHY_RX_EQ_VAL_2 0x8000 +#define USB_PHY_RX_EQ_VAL_3 0x8004 +#define USB_PHY_RX_EQ_VAL_4 0x800C + /* Supplemental Configuration Unit */ struct ccsr_scfg { u32 dpslpcr;