| Message ID | 20170904104655.29103-8-ran.wang_1@nxp.com |
|---|---|
| State | Accepted |
| Delegated to: | York Sun |
| Headers | show |
| Series | [U-Boot,v5,1/9] armv8: Add scfg_clrsetbits_32(), scfg_clrbits_32() | expand |
On 09/04/2017 04:04 AM, Ran Wang wrote: > Low Frequency Periodic Singaling (LFPS) Peak-to-Peak Differential > Output Voltage Test Compliance fails using default transmitter settings > > Change config of transmitter signal swings by setting register > PCSTXSWINGFULL to 0x47 to pass compliance tests. > > Signed-off-by: Sriram Dash <sriram.dash@nxp.com> > Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> > Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> > Signed-off-by: Ran Wang <ran.wang_1@nxp.com> > --- > Change in v5: > Use clrsetbits_be32() instead. > > Change in v4: > Update commit message about register setting. > Rename USB_PCSTXSWINGFULL to SCFG_USB_PCSTXSWINGFULL. > > Change in v3: > - none > > Change in v2: > In function erratum_a008997(): > 1.Put a blank line after variable declaration. Reordered Kconfig options. Applied to fsl-qoriq master. Thanks. York
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index f09766cf03..ee09dd6fed 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -7,6 +7,7 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 + select SYS_FSL_ERRATUM_A008997 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR_BE if SYS_FSL_DDR @@ -64,6 +65,11 @@ config SYS_FSL_ERRATUM_A009798 help Workaround for USB PHY erratum A009798 +config SYS_FSL_ERRATUM_A008997 + bool + help + Workaround for USB PHY erratum A008997 + config SYS_FSL_SRDS_1 bool diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index a0e3c85421..f409ad7f44 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -81,6 +81,18 @@ static void erratum_a009798(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */ } +static void erratum_a008997(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008997 + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; + + clrsetbits_be32(scfg + SCFG_USB3PRM2CR / 4, + SCFG_USB_PCSTXSWINGFULL_MASK, + SCFG_USB_PCSTXSWINGFULL_VAL); +#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ +} + + void s_init(void) { } @@ -170,6 +182,7 @@ int arch_soc_init(void) /* Erratum */ erratum_a009008(); erratum_a009798(); + erratum_a008997(); return 0; } diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 5762d3308a..e5c06170da 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -177,6 +177,9 @@ struct ccsr_gur { #define SCFG_USB3PRM1CR 0x070 #define SCFG_USB_TXVREFTUNE 0x9 #define SCFG_USB_SQRXTUNE_MASK 0x7 +#define SCFG_USB3PRM2CR 0x074 +#define SCFG_USB_PCSTXSWINGFULL_MASK 0x0000FE00 +#define SCFG_USB_PCSTXSWINGFULL_VAL 0x00008E00 /* Supplemental Configuration Unit */ struct ccsr_scfg {