From patchwork Mon Aug 28 15:25:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jan_L=C3=BCbbe?= X-Patchwork-Id: 806632 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xgwZT2m5wz9sNn for ; Tue, 29 Aug 2017 01:25:37 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751270AbdH1PZf (ORCPT ); Mon, 28 Aug 2017 11:25:35 -0400 Received: from metis.ext.4.pengutronix.de ([92.198.50.35]:60367 "EHLO metis.ext.4.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751161AbdH1PZe (ORCPT ); Mon, 28 Aug 2017 11:25:34 -0400 Received: from dude.hi.pengutronix.de ([2001:67c:670:100:1d::7]) by metis.ext.pengutronix.de with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.84_2) (envelope-from ) id 1dmLus-00080v-Cb; Mon, 28 Aug 2017 17:25:30 +0200 Received: from jlu by dude.hi.pengutronix.de with local (Exim 4.89) (envelope-from ) id 1dmLur-0006O5-KI; Mon, 28 Aug 2017 17:25:29 +0200 From: Jan Luebbe To: Gregory Clement , Andrew Lunn , Thomas Petazzoni , Jason Cooper Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, Jan Luebbe Subject: [PATCH 2/2] PCI: mvebu: Check DRAM window size Date: Mon, 28 Aug 2017 17:25:17 +0200 Message-Id: <20170828152517.24506-3-jlu@pengutronix.de> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170828152517.24506-1-jlu@pengutronix.de> References: <20170828152517.24506-1-jlu@pengutronix.de> X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::7 X-SA-Exim-Mail-From: jlu@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-pci@vger.kernel.org Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The sum of the DRAM windows may exceed 4GB (at least on Armada XP). Return an error in that case. Signed-off-by: Jan Luebbe --- drivers/pci/host/pci-mvebu.c | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c index f353a6eb2f01..5d74af81d104 100644 --- a/drivers/pci/host/pci-mvebu.c +++ b/drivers/pci/host/pci-mvebu.c @@ -206,10 +206,10 @@ static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr) * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks * WIN[0-3] -> DRAM bank[0-3] */ -static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) +static int mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) { const struct mbus_dram_target_info *dram; - u32 size; + u64 size; int i; dram = mv_mbus_dram_info(); @@ -252,19 +252,32 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) if ((size & (size - 1)) != 0) size = 1 << fls(size); + if (size > 0x100000000) { + dev_err(&port->pcie->pdev->dev, + "Could not configure DRAM window (too large): 0x%llx\n", + size); + + return -EINVAL; + } + /* Setup BAR[1] to all DRAM banks. */ mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1)); mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1)); mvebu_writel(port, ((size - 1) & 0xffff0000) | 1, PCIE_BAR_CTRL_OFF(1)); + + return 0; } -static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) +static int mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) { u32 cmd, mask; + int ret; /* Point PCIe unit MBUS decode windows to DRAM space. */ - mvebu_pcie_setup_wins(port); + ret = mvebu_pcie_setup_wins(port); + if (ret) + return ret; /* Master + slave enable. */ cmd = mvebu_readl(port, PCIE_CMD_OFF); @@ -277,6 +290,8 @@ static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) mask = mvebu_readl(port, PCIE_MASK_OFF); mask |= PCIE_MASK_ENABLE_INTS; mvebu_writel(port, mask, PCIE_MASK_OFF); + + return 0; } static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port, @@ -882,7 +897,9 @@ static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys) if (!port->base) continue; - mvebu_pcie_setup_hw(port); + err = mvebu_pcie_setup_hw(port); + if (err) + return 0; } return 1;