| Message ID | 20170828121638.13751-1-thomas.petazzoni@free-electrons.com |
|---|---|
| State | Deferred |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | [U-Boot] serial: serial_sh: take into account port->clk_mode for SH7785/7786 | expand |
Hello, On Mon, 28 Aug 2017 14:16:38 +0200, Thomas Petazzoni wrote: > In the SH7785/SH7786 case, the SCSCR value is harcoded to be 0x3a, > which means bits CKE1/CKE0 have the value 10b. This tells the SCIF > that the "External clock/SCIF_SCK pin functions as clock input". > > However, this is not the case in all designs, and it's the purpose of > the clk_mode = EXT_CLK to indicate such a setting. > > In order for the serial_sh driver to work on a SH7786 platform that > does not use SCIF_SCK as a clock input, we have to adjust the > SCSCR_INIT value, to have CKE1/CKE0 set to 00b. This is similar to > what is done for other SH platforms. > > Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Any comments on this patch ? Thanks, Thomas
Hi, 2017-09-14 7:27 GMT+09:00 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>: > Hello, > > On Mon, 28 Aug 2017 14:16:38 +0200, Thomas Petazzoni wrote: >> In the SH7785/SH7786 case, the SCSCR value is harcoded to be 0x3a, >> which means bits CKE1/CKE0 have the value 10b. This tells the SCIF >> that the "External clock/SCIF_SCK pin functions as clock input". >> >> However, this is not the case in all designs, and it's the purpose of >> the clk_mode = EXT_CLK to indicate such a setting. >> >> In order for the serial_sh driver to work on a SH7786 platform that >> does not use SCIF_SCK as a clock input, we have to adjust the >> SCSCR_INIT value, to have CKE1/CKE0 set to 00b. This is similar to >> what is done for other SH platforms. >> >> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> > > Any comments on this patch ? Sorry, reply is too late. Applied, thanks. > > Thanks, > > Thomas > -- > Thomas Petazzoni, CTO, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com Best regards, Nobuhiro
Hello, On Sat, 23 Sep 2017 07:19:40 +0900, Nobuhiro Iwamatsu wrote: > Sorry, reply is too late. > > Applied, thanks. Thanks! Do you have any suggestion/comments about: Subject: [U-Boot] I/O accessors on SuperH and endianness Date: Mon, 28 Aug 2017 14:32:49 +0200 and: Subject: [U-Boot] Initializing global_data on SuperH before board_init_f() ? Date: Tue, 15 Aug 2017 23:07:30 +0200 Thanks! Thomas
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 4d27122..d7bbd1a 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -184,7 +184,8 @@ struct uart_port { # define SCSPTR4 0xffee0024 /* 16 bit SCIF */ # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ # define SCIF_ORER 0x0001 /* Overrun error bit */ -# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ +# define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x3a : 0x38) + /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ #elif defined(CONFIG_CPU_SH7201) || \ defined(CONFIG_CPU_SH7203) || \ defined(CONFIG_CPU_SH7206) || \
In the SH7785/SH7786 case, the SCSCR value is harcoded to be 0x3a, which means bits CKE1/CKE0 have the value 10b. This tells the SCIF that the "External clock/SCIF_SCK pin functions as clock input". However, this is not the case in all designs, and it's the purpose of the clk_mode = EXT_CLK to indicate such a setting. In order for the serial_sh driver to work on a SH7786 platform that does not use SCIF_SCK as a clock input, we have to adjust the SCSCR_INIT value, to have CKE1/CKE0 set to 00b. This is similar to what is done for other SH platforms. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> --- drivers/serial/serial_sh.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)