[v7,1/2] mtd: spi-nor: add a quad_enable callback in struct flash_info

Message ID 1503885509-25335-1-git-send-email-andy.yan@rock-chips.com
State Accepted
Delegated to: Cyrille Pitchen
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Series
  • [v7,1/2] mtd: spi-nor: add a quad_enable callback in struct flash_info
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Commit Message

Andy Yan Aug. 28, 2017, 1:58 a.m.
Some manufacturers may use different bit to set QE on different
memories.

The GD25Q256 from GigaDevice is an example, which uses S6(bit 6
of the Status Register-1) to set QE, which is different with
other supported memories from GigaDevice that use S9(bit 1 of
the Status Register-2). This makes it is impossible to select
the quad enable method by distinguishing the MFR. This patch
introduce a quad_enable function which can be set per memory
in the flash_info list table.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>

---

Changes in v7:
- fix some typos.

Changes in v6:
- split the quad_enable callback to a single patch
- adjust the columns per line of the commit message.

Changes in v5:
- set quad_enable in flash_info list, thanks the guidance by Cyrille.

Changes in v4:
- add SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB

Changes in v3:
- rebase on top of spi-nor tree
- add SPI_NOR_4B_OPCODES flag

Changes in v2:
- drop one line unnecessary modification

 drivers/mtd/spi-nor/spi-nor.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

Comments

Cyrille Pitchen Oct. 10, 2017, 4:42 p.m. | #1
Le 28/08/2017 à 03:58, Andy Yan a écrit :
> Some manufacturers may use different bit to set QE on different
> memories.
> 
> The GD25Q256 from GigaDevice is an example, which uses S6(bit 6
> of the Status Register-1) to set QE, which is different with
> other supported memories from GigaDevice that use S9(bit 1 of
> the Status Register-2). This makes it is impossible to select
> the quad enable method by distinguishing the MFR. This patch
> introduce a quad_enable function which can be set per memory
> in the flash_info list table.
> 
> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>

Applied to the spi-nor/next branch of l2-mtd

Thanks!
> 
> ---
> 
> Changes in v7:
> - fix some typos.
> 
> Changes in v6:
> - split the quad_enable callback to a single patch
> - adjust the columns per line of the commit message.
> 
> Changes in v5:
> - set quad_enable in flash_info list, thanks the guidance by Cyrille.
> 
> Changes in v4:
> - add SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB
> 
> Changes in v3:
> - rebase on top of spi-nor tree
> - add SPI_NOR_4B_OPCODES flag
> 
> Changes in v2:
> - drop one line unnecessary modification
> 
>  drivers/mtd/spi-nor/spi-nor.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index cf1d4a1..3b94308 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -89,6 +89,8 @@ struct flash_info {
>  #define NO_CHIP_ERASE		BIT(12) /* Chip does not support chip erase */
>  #define SPI_NOR_SKIP_SFDP	BIT(13)	/* Skip parsing of SFDP tables */
>  #define USE_CLSR		BIT(14)	/* use CLSR command */
> +
> +	int	(*quad_enable)(struct spi_nor *nor);
>  };
>  
>  #define JEDEC_MFR(info)	((info)->id[0])
> @@ -2388,6 +2390,15 @@ static int spi_nor_init_params(struct spi_nor *nor,
>  			params->quad_enable = spansion_quad_enable;
>  			break;
>  		}
> +
> +		/*
> +		 * Some manufacturer like GigaDevice may use different
> +		 * bit to set QE on different memories, so the MFR can't
> +		 * indicate the quad_enable method for this case, we need
> +		 * set it in flash info list.
> +		 */
> +		if (info->quad_enable)
> +			params->quad_enable = info->quad_enable;
>  	}
>  
>  	/* Override the parameters with data read from SFDP tables. */
>

Patch

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index cf1d4a1..3b94308 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -89,6 +89,8 @@  struct flash_info {
 #define NO_CHIP_ERASE		BIT(12) /* Chip does not support chip erase */
 #define SPI_NOR_SKIP_SFDP	BIT(13)	/* Skip parsing of SFDP tables */
 #define USE_CLSR		BIT(14)	/* use CLSR command */
+
+	int	(*quad_enable)(struct spi_nor *nor);
 };
 
 #define JEDEC_MFR(info)	((info)->id[0])
@@ -2388,6 +2390,15 @@  static int spi_nor_init_params(struct spi_nor *nor,
 			params->quad_enable = spansion_quad_enable;
 			break;
 		}
+
+		/*
+		 * Some manufacturer like GigaDevice may use different
+		 * bit to set QE on different memories, so the MFR can't
+		 * indicate the quad_enable method for this case, we need
+		 * set it in flash info list.
+		 */
+		if (info->quad_enable)
+			params->quad_enable = info->quad_enable;
 	}
 
 	/* Override the parameters with data read from SFDP tables. */