From patchwork Wed Jan 26 16:38:30 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Hellstrom X-Patchwork-Id: 80525 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 31E9CB7116 for ; Thu, 27 Jan 2011 03:38:45 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752830Ab1AZQio (ORCPT ); Wed, 26 Jan 2011 11:38:44 -0500 Received: from mail176c2.megamailservers.com ([69.49.111.76]:57121 "EHLO mail176c2.megamailservers.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752732Ab1AZQio (ORCPT ); Wed, 26 Jan 2011 11:38:44 -0500 X-POP-User: ekergarn.gaisler.com Received: from localhost.localdomain (static-92-33-28-242.sme.bredbandsbolaget.se [92.33.28.242]) by mail176c2.megamailservers.com (8.13.6/8.13.1) with ESMTP id p0QGcdvk010799; Wed, 26 Jan 2011 11:38:40 -0500 From: Daniel Hellstrom To: davem@davemloft.net Cc: sparclinux@vger.kernel.org Subject: [PATCH 1/2] SPARC32: implement SMP IPIs using the generic functions Date: Wed, 26 Jan 2011 17:38:30 +0100 Message-Id: <1296059911-22861-1-git-send-email-daniel@gaisler.com> X-Mailer: git-send-email 1.5.4 X-CSC: 0 X-CHA: v=1.1 cv=7GFoO/wu22Xu7f+7cd9V9wY/biOPJIupRAMVre9JRXg= c=1 sm=1 a=txLtX8AZOPAA:10 a=jXKJviUpWSOlMmIvGrHOfw==:17 a=ebG-ZW-8AAAA:8 a=kc_Rn-JUsL9TNS9VS14A:9 a=o5A0t5tQ4gmD07JxvvYA:7 a=gylZ7AwukMFnfEdr3ENGCPL2LdkA:4 a=cCYF7-FHeg4A:10 a=jXKJviUpWSOlMmIvGrHOfw==:117 Sender: sparclinux-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: sparclinux@vger.kernel.org The current SPARC32 SMP IPI generation is implemented the cross call function. The cross call function uses IRQ15 the NMI, this is has the effect that IPIs will interrupt IRQ critical areas and hang the system. Typically on/after spin_lock_irqsave calls can be aborted. The cross call functionality must still exist to flush cache/TLBS. This patch provides CPU models a custom way to implement generation of IPIs on the generic code's request. The typical approach is to generate an IRQ for each IPI case. After this patch each SPARC32 SMP CPU model needs to implement IPIs in order to function properly. Signed-off-by: Daniel Hellstrom --- arch/sparc/Kconfig | 1 + arch/sparc/include/asm/smp_32.h | 15 ++------------- arch/sparc/kernel/smp_32.c | 34 +++++++++++++++++++++++++++++++++- 3 files changed, 36 insertions(+), 14 deletions(-) diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index e48f471..0e7b361 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -25,6 +25,7 @@ config SPARC select HAVE_DMA_ATTRS select HAVE_DMA_API_DEBUG select HAVE_ARCH_JUMP_LABEL + select USE_GENERIC_SMP_HELPERS if SMP config SPARC32 def_bool !64BIT diff --git a/arch/sparc/include/asm/smp_32.h b/arch/sparc/include/asm/smp_32.h index 841905c..a56961c 100644 --- a/arch/sparc/include/asm/smp_32.h +++ b/arch/sparc/include/asm/smp_32.h @@ -67,19 +67,8 @@ static inline void xc4(smpfunc_t func, unsigned long arg1, unsigned long arg2, unsigned long arg3, unsigned long arg4) { smp_cross_call(func, cpu_online_map, arg1, arg2, arg3, arg4); } -static inline int smp_call_function(void (*func)(void *info), void *info, int wait) -{ - xc1((smpfunc_t)func, (unsigned long)info); - return 0; -} - -static inline int smp_call_function_single(int cpuid, void (*func) (void *info), - void *info, int wait) -{ - smp_cross_call((smpfunc_t)func, cpumask_of_cpu(cpuid), - (unsigned long) info, 0, 0, 0); - return 0; -} +extern void arch_send_call_function_single_ipi(int cpu); +extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); static inline int cpu_logical_map(int cpu) { diff --git a/arch/sparc/kernel/smp_32.c b/arch/sparc/kernel/smp_32.c index 91c10fb..a1bb3a8 100644 --- a/arch/sparc/kernel/smp_32.c +++ b/arch/sparc/kernel/smp_32.c @@ -125,13 +125,45 @@ struct linux_prom_registers smp_penguin_ctable __cpuinitdata = { 0 }; void smp_send_reschedule(int cpu) { - /* See sparc64 */ + /* + * CPU model dependent way of implementing IPI generation targeting + * a single CPU. The trap handler needs only to do trap entry/return + * to call schedule. + */ + switch (sparc_cpu_model) { + default: + BUG(); + } } void smp_send_stop(void) { } +void arch_send_call_function_single_ipi(int cpu) +{ + /* + * CPU model dependent way of implementing IPI generation targeting + * a single CPU + */ + switch (sparc_cpu_model) { + default: + BUG(); + } +} + +void arch_send_call_function_ipi_mask(const struct cpumask *mask) +{ + /* + * CPU model dependent way of implementing IPI generation targeting + * a set of CPUs + */ + switch (sparc_cpu_model) { + default: + BUG(); + } +} + void smp_flush_cache_all(void) { xc0((smpfunc_t) BTFIXUP_CALL(local_flush_cache_all));